參數(shù)資料
型號(hào)： MSM82C55A-2RS
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 24 I/O, PIA-GENERAL PURPOSE, PDIP40
封裝： 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40
文件頁(yè)數(shù)： 8/26頁(yè)
文件大小： 173K
代理商： MSM82C55A-2RS
16/26
Semiconductor
MSM82C55A-2RS/GS/VJS
(b) When group A is mode 1 input and group B is mode 1 output.
0
1
1/0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Selection of I/O of PC6 and PC7
when not defined as a control pin.
STBA
IBFA
INTRA
I/O
PC4
PC5
PC3
PC6, PC7
PA7 - PA0
Group A: Mode 1 Input
Group B: Mode 1 Output
OBFB
ACKB
INTRB
PC1
PC2
PC0
PB7 - PB0
8
RD
2
1 = Input
0 = Output
8
2
WR
3. Mode 2 (Strobe bidirectional bus I/O operation)
In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This
operation is akin to a combination between input and output operations. Port C waits for
the control signal in this case, too. Mode 2 is available only for group A, however.
Next, a description is made on mode 2.
OBF (Output buffer full flag output)
This signal when turned to low level indicates that data has been written to the internal
output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the
high impedance status and the data is not yet output to the outside. This signal turns to low
level at the rising edge of the WR and high level at the falling edge of the ACK.
ACK (Acknowledge input)
When a low level signal is input to this pin, the high impedance status of port A is cleared,
the buffer is enabled, and the data written to the internal output latch is output to port A.
When the input returns to high level, port A is made into the high impedance status.
STB (Strobe input)
When this signal turns to low level, the data output to the port from the pin is fetched into
the internal input latch. The data is output to the data bus upon receipt of the RD signal from
the CPU, but it remains in the high impedance status until then.
IBF (Input buffer full flag output)
This signal when turned to high level indicates that data from the pin has been fetched into
the input latch. This signal turns to high level at the falling edge of the STB and low level
at the rising edge of the RD.
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