參數(shù)資料
型號(hào)： MSM82C59A-2RS
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類(lèi)： 中斷控制器
英文描述： 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDIP28
封裝： 0.600 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 269K
代理商： MSM82C59A-2RS
14/29
Semiconductor
MSM82C59A-2RS/GS/JS
FEDL82C59A-2-03
(ii) Operation Command Words (OCW1 thru OCW3)
These commands are used in operating the MSM82C59A-2 in the following modes.
a. Fully Nested Mode
b. Rotating Priority Mode
c. Special Mask Mode
d. Polled Mode
The OCW can be written into the MSM82C59A-2 any time after initialization has been
completed.
(5) Initialization Command Words (ICW1 thru ICW4)
When a command is issued with D4 = 1 and A0 = 0, it is always regarded as an Initialization
Command Word 1 (ICW1). Starting of the initialization sequence by ICW1 results in
automatic execution of the following steps.
a. The edge sense circuit is reset, and a low to high transition is necessary to generate an
interrupt.
b. The interrupt mask register is cleared.
c. The IR7 input is assigned priority 7 (lowest priority)
d. Slave mode address is set to 7.
e. The Special Mask Mode is cleared, and the Status Read is set to IRR.
f. All ICW4 functions are cleared if IC4 = 0, resulting in a change to Non-Buffered mode, no-
Auto EOI, and 85 mode.
Note: Master/slave in ICW4 can only be used in buffered mode.
(i)
Initialization Command Words 1 and 2 (ICW1 and ICW2)
A4 thru A15: (Starting address of interrupt service routines)
In 85 mode, 8 request levels CALL 8 locations at equivalent intervals in
the memory. The memory location interval can be set at this stage to 4 or
8 by program. (ADI)Hence, either 32 or 64 bytes/page respectively are
used in the 8 routines.
The address format is 2 bytes long (A0 thru A15). When the routine
interval is 4, A0 thru A4 are inserted automatically by the MSM82C59A-
2, and A5 thru A15 are programmed externally. When the interval is 8,
on the other hand, A0 thru A5 are inserted automatically by the
MSM82C59A-2, and A6 thru A15 are programmed externally. In 86
mode, T3 thru T7 are inserted in the 5 most significant bits of the vector
type. And the MSM82C59A-2 sets the 3 least significant bits according to
the interrupt level. A0 thru A10 are ignored, and the ADI (address
interval) has no effect.
LTIM:
The MSM82C59A-2 is operated in level triggered mode when LTIM = 1,
and the interrupt input edge circuit becomes disabled.
ADI:
Designation of the CALL address interval. Interval = 4 when ADI = 1,
and interval = 8 when ADI = 0.
SNGL:
SNGL = 1 indicates the existence of only one MSM82C59A-2 in the
system. ICW3 is not required when SNGL = 1.
IC4:
ICW4 is required when this bit is set, but not required when IC4 = 0.
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