- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68017 > MSM83C154S-XXXRS (LAPIS SEMICONDUCTOR CO LTD) 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 PDF資料下載
參數(shù)資料
| 型號： | MSM83C154S-XXXRS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 5/41頁 |
| 文件大?。?/td> | 274K |
| 代理商： | MSM83C154S-XXXRS |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
12/40
MSM80C154S/83C154S
Semiconductor
Power control register (PCON)
IDLE mode is set when this bit is set to "1". CPU operations are stopped when
IDLE mode is set, but XTAL12, timer/counters 0, 1 and 2, the interrupt circuits,
and the serial port remain active. IDLE mode is cancelled when the CPU is reset
or when an interrupt is generated.
NAME
ADDRESS
MSB
LSB
76543210
BIT LOCATION
FLAG
FUNCTION
PCON
87H
SMOD
HPD
RPD
—
GF1
GF0
PD
IDL
PCON.0
IDL
PD mode is set when this bit is set to "1". CPU operations and XTAL12 are
stopped when PD mode is set. PD mode is cancelled when the CPU is reset or
when an interrupt is generated.
PCON.1
PD
General purpose bit.
PCON.2
GF0
General purpose bit.
PCON.3
GF1
Reserved bit. The output data is "1", if the bit is read.
PCON.4
—
This bit is used to specify cancellation of CPU power down mode (IDLE or PD) by an
interrupt signal.
Power-down mode cannot be cancelled by an interrupt signal if the interrupt is not
enabled by IE (interrupt enable register) when this bit is "0".
If the interrupt flag is set to "1" by an interrupt request signal when this bit is
"1" (even if interrupt is disabled), the program is executed from the next address
of the power-down-mode setting instruction.
The flag is reset to "0" by software.
PCON.5
RPD
The hard power-down setting mode in enabled when this bit is set to "1".
If the level of the power failure detect signal applied to the HPDI pin (pin 3.5)
is changed from "1" to "0" when this bit is "1", XTAL12 oscillation is stopped and
the system is put into hard power down mode. HPD mode is cancelled when the
CPU is reset.
PCON.6
HPD
When the timer/counter 1 carry signal is used as a clock in mode 1, 2 or 3 of
the serial port, this bit has the following functions.
The serial port operation clock is reduced by 1/2 when the bit is "0" for delayed
processing. When the bit is "1", the serial port operation clock is normal
for faster processing.
PCON.7
SMOD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM83C154S-XXXGS-2K | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
| MSM80C154SJS | 8-BIT, 24 MHz, MICROCONTROLLER, PQCC44 |
| MSM80C154SRS | 8-BIT, 24 MHz, MICROCONTROLLER, PDIP40 |
| MSM80C154SGS-2K | 8-BIT, 24 MHz, MICROCONTROLLER, PQFP44 |
| MSM85C154HVS | 8-BIT, MROM, 22 MHz, MICROCONTROLLER, CDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM8512C-020 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 Static RAM Issue 5.2 April 2001 |
| MSM8521CB-020 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 Static RAM Issue 5.2 April 2001 |
| MSM8521CB-48D | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 Static RAM Issue 5.2 April 2001 |
| MSM8521CBI-020 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 Static RAM Issue 5.2 April 2001 |
| MSM8521CBI-48D | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 Static RAM Issue 5.2 April 2001 |
發(fā)布緊急采購，3分鐘左右您將得到回復。