參數(shù)資料
型號: MSM9000B-01AV-Z-XX
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 顯示控制器
英文描述: 16 X 60 DOTS DOT MAT LCD DSPL CTLR, UUC
封裝: 35 MM, TCP
文件頁數(shù): 20/39頁
文件大小: 389K
代理商: MSM9000B-01AV-Z-XX
Semiconductor
27/39
MSM9000B-xx
FEDL9000B-01
Flowchart at Power-on (serial interface)
When the stage to be selected is already determined, contrast can be adjusted before the
display is turned on (for example, at the same time as when mode is set).
After a command or display data is input, check for busy data. Make sure that the busy data
("H") has changed to not-busy data ("L") before making the next input.
Turn on the power
Input a reset
CS="L"
SOE/D, D0="1"
Wait for 10 clocks
Set modes for SF, BKCG1/0,
BPC, and ABLC
LOT, I1="1", I0="1"
AINC 48 times
LOT, I1="0", I0="0"
DISP, D4="X", D0="1"
Perform ordinary operation
Has data to be displayed
on the initial screen been
input?
5ms, external, or power-on reset
Chip enable.
SO output is enabled to detect busy signal.
Insert a wait only in processing the SOE/D command.
(By busy signal detection for subsequent inputs).
Change the settings after a reset, if necessary.
Set the load option. The blank code is written and
blinking is disabled each time AINC is executed.
RAM data is cleared.
The load option is cleared.
The display is turned on. The initial screen is displayed.
Set D4 according to the display.
YES
NO
Input data to be displayed
on the initial screen
Input a reset after the VDD–VSS level exceeds 2.5V.
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