參數(shù)資料
型號: MSM9005-XXGS-BK
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 顯示控制器
英文描述: 8 X 65 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 6/30頁
文件大?。?/td> 295K
代理商: MSM9005-XXGS-BK
Semiconductor
MSM9005-xx
14/30
FEDL9005-03
How to Read Display Data
Display data is output sequentially from MSB in 8-bit units (MSB first).
Setting S = "1" by the SOE/D command after setting the CS pin at "H" level enables the output
of display data from the SO pin.
Setting the CS pin at "L" level or setting S = "0" by the SOE/D command sets the SO pin to high
impedance and disables output of display data.
CGARAM or ABRAM data corresponding to the address pointer value is output.
Display data is output from MSB on the falling edge of the shift clock that is input to the SHT
pin, as shown in the figure below.
Read timing is shown below.
(Example) Reading by AINC command The wait time of 21
× 1/fOSC is required
21 x 1/fOSC
Don't Care
11*0000 1
100*1*
1
*
100*1*1*
CS
C/D
SHT
Address
pointer
SI
SO
MSB
LSB
Display data at address
00h of CGA RAM
MSB
LSB
Display data at address
01h of CGA RAM
"HZ"
00h
WAIT
01h
SOE/D command
AINC command
0
RD4 RD3 RD2 RD1 RD
0
RD4 RD3 RD2 RD1 RD
0
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