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參數(shù)資料
| 型號： | MSM9225GA-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 9/74頁 |
| 文件大小： | 487K |
| 代理商： | MSM9225GA-2K |
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Semiconductor
MSM9225
17/73
BRP5
BRP3
BRP2
BRP1
BRP0
00
0
1
00
0
11
1
0
BTL cycle time
1
BRP4
0
0
1
11
1
1X system clock cycle
2X system clock cycle
63X system clock cycle
64X system clock cycle
(1) Baud rate prescaler: BRP5 to BRP0
This is a 6-bit prescaler to set the BTL cycle time and SJW of the basic clock for
communication operation.
The relationship between the bit content and BTL is as follows:
At reset, BRP5 to BRP0 are set to "000000".
The BTL cycle time is given by the following operation.
BTL cycle time = 2 (25 BRP5 + 24 BRP4 + 23 BRP3 + 22 BRP2 + 21 BRP1 + BRP0
+ 1)/fOSC
*)
System clock is 1/2 division of oscillation frequency.
fOSC is the oscillation frequency.
(2)
SJW: SJWA, SJWB
This is a 2-bit register to set SJW.
The relationship between bit content and SJW is as follows:
At reset, SJWA and SJWB are set to “00”.
SJWB
SJWA
SJW1, SJW2
00
1 BTL cycle
01
2 BTL cycle
10
3 BTL cycle
11
4 BTL cycle
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