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參數(shù)資料
| 型號： | MSP430A017IPNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封裝： | GREEN, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 5/73頁 |
| 文件大?。?/td> | 1185K |
| 代理商： | MSP430A017IPNR |
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MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380A APRIL 2004 REVISED SEPTEMBER 2004
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature
Number SLAU056.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430FG43x family of devices is supported by the FLL+ module that includes support
for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6
s. The FLL+ module
provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
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