參數(shù)資料
型號： MSP430A059IRTDT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQCC64
封裝： GREEN, PLASTIC, QFN-64
文件頁數(shù)： 16/58頁
文件大?。?/td> 1167K
代理商： MSP430A059IRTDT
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340H MAY 2001 REVISED APRIL 2007
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VCC
MIN
TYP
MAX
UNIT
V
Positive going input threshold voltage
2.2 V
1.1
1.5
V
VIT+
Positive-going input threshold voltage
3 V
1.5
1.9
V
Negative going input threshold voltage
2.2 V
0.4
0.9
V
VIT
Negative-going input threshold voltage
3 V
0.9
1.3
V
Input voltage hysteresis (V
V
)
2.2 V
0.3
1.1
V
Vhys
Input voltage hysteresis (VIT+ VIT)
3 V
0.45
1
V
standard inputs RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VIL
Low-level input voltage
2 2 V/3 V
VSS
VSS+0.6
V
VIH
High-level input voltage
2.2 V/3 V
0.8
×VCC
VCC
V
inputs Px.x, TAx/TAx.x
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Port P1, P2: P1.x to P2.x, External
2.2 V/3 V
1.5
cycle
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, External
trigger signal for the interrupt flag,
(N
2.2 V
62
ns
(int)
pg
gg
g
p
g,
(see Note 1)
3 V
50
ns
t()
Timer A capture timing
TAx/TAx y
2.2 V
62
ns
t(cap)
Timer_A, capture timing
TAx/TAx.y
3 V
50
ns
f
Timer_A clock frequency externally
TACLK/TAxCLK INCLK t
=t
2.2 V
8
MHz
f(TAext)
Timer_A clock frequency externally
applied to pin
TACLK/TAxCLK, INCLK t(H) = t(L)
3 V
10
MHz
f
Timer A clock frequency
SMCLK or ACLK signal selected
2.2 V
8
MHz
f(TAint)
Timer_A clock frequency
SMCLK or ACLK signal selected
3 V
10
MHz
NOTES:
1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
MIN
NOM
MAX
UNIT
Ilkg(P1.x)
Port P1
V(P1.x) (see Note 2)
±50
Ilkg(P2.x)
Port P2
V(P2.x) (see Note 2)
±50
Ilkg(P3.x)
Leakage current
Port P3
V(P3.x) (see Note 2)
2 2 V/3 V
±50
nA
Ilkg(P4.x)
Leakage current
Port P4
V(P4.x) (see Note 2)
2.2 V/3 V
±50
nA
Ilkg(P5.x)
Port P5
V(P5.x) (see Note 2)
±50
Ilkg(P6.x)
Port P6
V(P6.x) (see Note 2)
±50
NOTES:
1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
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