參數(shù)資料
型號(hào): MSP430AFE231IPW
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, RISC MICROCONTROLLER, PDSO24
封裝: GREEN, PLASTIC, TSSOP-24
文件頁(yè)數(shù): 47/47頁(yè)
文件大小: 900K
代理商: MSP430AFE231IPW
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A
– NOVEMBER 2010 – REVISED MARCH 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 5. Interrupt Vector Addresses
SYSTEM
INTERRUPT SOURCE
INTERRUPT FLAG
WORD ADDRESS
PRIORITY
INTERRUPT
Power up
PORIFG
External reset
RSTIFG
Watchdog
WDTIFG
Reset
0FFFEh
15, highest
Flash key violation
KEYV
PC out-of-range(1)
(2)
NMI
NMIIFG
(Non)maskable,
Oscillator fault
OFIFG
(Non)maskable,
0FFFCh
14
Flash memory access violation
ACCVIFG (2) (3)
(Non)maskable
0FFFAh
13
SD24CCTLx SD24OVIFG,
SD24_A
Maskable
0FFF8h
12
SD24CCTLx SD24IFG(2) (4)
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
0FFEEh
7
Timer_A3
TA0CCR0 CCIFG(4)
Maskable
0FFECh
6
TA0CCR1 CCIFG,
Timer_A3
TA0CCR2 CCIFG,
Maskable
0FFEAh
5
TA0CTL TAIFG (2) (4)
I/O Port P1 (eight flags)
P1IFG.0 to P1IFG.7(2) (4)
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
I/O Port P2 (three flags)
P2IFG.0 to P2IFG.2(2) (4)
Maskable
0FFE2h
1
0FFE0h
0, lowest
(1)
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2)
Multiple source flags
(3)
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4)
Interrupt flags are located in the module.
Copyright
2010–2011, Texas Instruments Incorporated
9
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