參數(shù)資料
型號(hào)： MSP430F1232IRHBT
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQCC32
封裝： PLASTIC, QFN-32
文件頁(yè)數(shù)： 20/52頁(yè)
文件大?。?/td> 1174K
代理商： MSP430F1232IRHBT
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D JANUARY 2002 REVISED AUGUST 2004
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
10-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
For specified performance of
ADC10SR = 0
0.450
6.3
fADC10CLK
For specified performance of
ADC10 linearity parameters
ADC10SR = 1
0.450
1.5
MHz
fADC10OSC
ADC10DIV=0,
fADC10CLK=fADC10OSC
VCC =
2.2 V/ 3V
3.7
6.3
MHz
t
Conversion time
Internal oscillator,
fADC10OSC = 3.7 MHz to
6.3 MHz
VCC =
2.2 V/ 3 V
2.06
3.51
s
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK or SMCLK:
ADC10SSEL
≠ 0
13
×ADC10DIV×
1/fADC10CLK
s
tADC10ON
Turn on settling time of
the ADC
(see Note 1)
100
ns
RS = 400 , RI = 2000 ,
VCC = 3 V
1400
tSample
Sampling time
RS = 400 , RI = 2000 ,
CI = 20 pF (see Note 2)
VCC = 2.2 V
1400
ns
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:
1. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately eight Tau (
τ) are needed to get an error of less than ±0.5 LSB.
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns. (ADC10SR = 0, n = ADC resolution = 10, RS = external source resistance)
tSample = ln(2n+1) x (RS + RI) x CI+ 2.5 s. (ADC10SR = 1, n = ADC resolution = 10, RS = external source resistance)
10-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
VCC
MIN
NOM
MAX
UNIT
1.4 V
≤ (VeREF+ VREF/VeREF) min ≤ 1.6 V
±1
EI
Integral linearity error
1.6 V < (VeREF+ VREF/VeREF) min ≤ [VCC]
2.2 V/3 V
±1
LSB
ED
Differential linearity
error
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF)
2.2 V/3 V
±1
LSB
EO
Offset error
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF),
Internal impedance of source RS < 100 ,
2.2 V/3 V
±2
±4
LSB
EG
Gain error
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF),
2.2 V/3 V
±1.1
±2
LSB
ET
Total unadjusted
error
(VeREF+ VREF/VeREF)min ≤ (VeREF+ VREF/VeREF),
2.2 V/3 V
±2
±5
LSB
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