參數(shù)資料
型號(hào): MSP430F2101IRGE
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQCC24
封裝: PLASTIC, QFN-24
文件頁(yè)數(shù): 30/95頁(yè)
文件大小: 1832K
代理商: MSP430F2101IRGE
MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547D -- JUNE 2007 -- REVISED APRIL 2010
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG, XIN, and XT2IN (see Note 6)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
0.45 VCC
0.75 VCC
VIT+
Positive-going input threshold voltage
2.2 V
1.0
1.65
V
VIT+
Positive going input threshold voltage
3V
1.35
2.25
V
0.25 VCC
0.55 VCC
VIT--
Negative-going input threshold voltage
2.2 V
0.55
1.2
V
VIT--
Negative going input threshold voltage
3V
0.75
1.65
V
Input voltage hysteresis (V
V )
2.2 V
0.2
1.0
V
Vhys
Input voltage hysteresis (VIT+ -- VIT--)
3V
0.3
1.0
V
RPull
Pullup/pulldown resistor
Pullup: VIN =VSS,
Pulldown: VIN =VCC
20
35
50
k
CI
Input Capacitance
VIN =VSS or VCC
5
pF
NOTE 6. XIN and XT2IN only in bypass mode
inputs -- ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
tint
External interrupt timing
Port P1, P2: P1.x to P2.x, external
trigger pulse width to set the interrupt
flag (see Note 1)
2.2 V/3 V
20
ns
t
Timer A Timer B capture timing
TA0, TA1, TA2
2.2 V
62
ns
tcap
Timer_A,Timer_B capture timing
TB0, TB1, TB2, TB3, TB4, TB5, TB6
3V
50
ns
fTAext
Timer_A,Timer_Bclock frequency externally
TACLK TBCLK INCLK: t
t
2.2 V
8
MHz
fTBext
Timer_A, Timer_B clock frequency externally
applied to pin
TACLK, TBCLK, INCLK: t(H) =t(L)
3V
10
MHz
fTAint
Timer A Timer B clock frequency
SMCLK or ACLK signal selected
2.2 V
8
MHz
fTBint
Timer_A,Timer_Bclock frequency
SMCLK or ACLK signal selected
3V
10
MHz
NOTE 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter
than t(int).
leakage current -- ports P1, P2, P3, P4, P5, and P6 (see Note 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
Ilkg(Px.x)
High impedance leakage current
See Notes 1 and 2
2.2 V/3 V
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of digital port pins is measured individually. The port pin is selected for input and the pullup/pull--down resistor is
disabled..
standard inputs -- RST/NMI
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VIL
Low-level input voltage
2.2 V/3 V
VSS
VSS +0.6
V
VIH
High-level input voltage
2.2 V/3 V
0.8 VCC
VCC
V
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