參數(shù)資料
型號(hào): MSP430F2131IDW
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PDSO20
封裝: GREEN, PLASTIC, SOIC-20
文件頁(yè)數(shù): 54/57頁(yè)
文件大?。?/td> 1276K
代理商: MSP430F2131IDW
MSP430x21x1
MIXED SIGNAL MICROCONTROLLER
SLAS439D -- SEPTEMBER 2004 -- REVISED SEPTEMBER 2010
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power--up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 4)
(non)-maskable,
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
Comparator_A+
CAIFG
maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
25
Timer_A3
TACCR2, TACCR1 CCIFG,
TAIFG (see Notes 2 and 3)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
0FFEAh
21
0FFE8h
20
I/O Port P2
(eight flags)
P2IFG.0toP2IFG.7
(see Notes 2 and 3)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0toP1IFG.7
(see Notes 2 and 3)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(see Note 5)
0FFDEh
15
(see Note 6)
0FFDCh to 0FFC0h
14 to 0, lowest
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
2. Multiple source flags
3. Interrupt flags are located in the module
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. This location is used as bootstrap loader security key (BSLSKEY).
A value of 0AA55h at this location disables the BSL completely.
A value of 0h disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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