參數(shù)資料
型號(hào): MSP430F247TRGC
廠(chǎng)商: TEXAS INSTRUMENTS INC
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, QCC64
封裝: PLASTIC, QFN-64
文件頁(yè)數(shù): 2/91頁(yè)
文件大小: 1246K
代理商: MSP430F247TRGC
MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547H
– JUNE 2007 – REVISED AUGUST 2011
Table 2. Terminal Functions, MSP430F23x (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
P6.3/A3
2
I/O
General-purpose digital I/O / analog input A3 - 12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O / analog input A4 - 12-bit ADC
P6.5/A5
4
I/O
General-purpose digital I/O / analog input A5 - 12-bit ADC
P6.6/A6
5
I/O
General-purpose digital I/O / analog input A6 - 12-bit ADC
P6.7/A7/SVSIN
6
I/O
General-purpose digital I/O / analog input A7 - 12-bit ADC/SVS input
XT2OUT
52
O
Output terminal of crystal oscillator XT2
XT2IN
53
I
Input port for crystal oscillator XT2
RST/NMI
58
I
Reset input, nonmaskable interrupt input, or bootstrap loader start (in flash devices)
TCK
57
I
Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start.
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
54
I/O
Test data output. TDO/TDI data output or programming data input terminal.
TMS
56
I
Test mode select. TMS is used as an input port for device programming and test.
VeREF+
10
I
Input for an external reference voltage
VREF+
7
O
Output of positive terminal of the reference voltage in the ADC12
Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external
VREF-/VeREF-
11
I
applied reference voltage
XIN
8
I
Input for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output for crystal oscillator XT1. Standard or watch crystals can be connected.
QFN Pad
NA
QFN package pad connection to DVSS recommended
10
Copyright
2007–2011, Texas Instruments Incorporated
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