參數(shù)資料
型號: MSP430F248TPMR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, LQFP-64
文件頁數(shù): 61/91頁
文件大?。?/td> 1246K
代理商: MSP430F248TPMR
MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547H
– JUNE 2007 – REVISED AUGUST 2011
12-Bit ADC, Timing Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
NOM
MAX UNIT
For specified performance of ADC12
fADC12CLK
2.2 V/3 V
0.45
5
6.3
MHz
linearity parameters
ADC12DIV = 0,
fADC12OSC
Internal ADC12 oscillator
2.2 V/3 V
3.7
5
6.3
MHz
fADC12CLK = fADC12OSC
CVREF+ ≥ 5 F, Internal oscillator,
2.2 V/3 V
2.06
3.51
s
fADC12OSC = 3.7 MHz to 6.3 MHz
tCONVERT
Conversion time
External fADC12CLK from ACLK, MCLK,
13
×
or SMCLK,
ADC12DIV
×
s
ADC12SSEL
0
1/fADC12CLK
Turn-on settling time of the
tADC12ON
See (2)
100
ns
ADC (1)
3 V
1220
RS = 400 ,RI = 1000 , CI = 30 pF,
tSample
Sampling time(1)
ns
τ = [RS +RI] × CI
(3)
2.2 V
1400
(1)
Limits verified by design
(2)
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(3)
Approximately ten Tau (
τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2
n+1) × (R
S + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
12-Bit ADC, Linearity Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
NOM
MAX
UNIT
1.4 V
≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V
±2
Integral linearity
EI
2.2 V/3 V
LSB
error
1.6 V
< (VeREF+ – VREF–/VeREF–) min ≤ VAVCC
±1.7
Differential linearity (VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
ED
2.2 V/3 V
±1
LSB
error
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
(VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
EO
Offset error
Internal impedance of source RS
< 100 ,
2.2 V/3 V
±2
±4
LSB
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
EG
Gain error
2.2 V/3 V
±1.1
±2
LSB
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
Total unadjusted
(VeREF+ -– VREF–/VeREF– )min ≤ (VeREF+ –VREF–/VeREF–),
ET
2.2 V/3 V
±2
±5
LSB
error
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
64
Copyright
2007–2011, Texas Instruments Incorporated
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