參數(shù)資料
型號： MSP430F4132IPMR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, MS-026, LQFP-64
文件頁數(shù)： 40/82頁
文件大小： 1562K
代理商： MSP430F4132IPMR
MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fUSCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% 10%
fSYSTEM MHz
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud)
(see Note 1)
2.2V /3 V
2
MHz
t
UART receive deglitch time
2.2 V
50
150
ns
t
UART receive deglitch time
(see Note 2)
3V
50
100
ns
NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI master mode) (see Figure 19 and Figure 20)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
fUSCI
USCI input clock frequency
SMCLK, ACLK
Duty cycle = 50% 10%
fSYSTEM
MHz
t
SOMI input data setup time
2.2 V
110
ns
tSU,MI
SOMI input data setup time
3V
75
ns
t
SOMI input data hold time
2.2 V
0
ns
tHD,MI
SOMI input data hold time
3V
0
ns
t
SIMO output data valid time
UCLK edgetoSIMOvalid,
2.2 V
30
ns
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid,
CL =20pF
3V
20
ns
NOTE:
f
UCxCLK
=
1
2t
LO∕HI
with
t
LO∕HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave’s parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 21 and Figure 22)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
tSTE,LEAD
STE lead time
STE low to clock
2.2 V/3 V
50
ns
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V
10
ns
tSTE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
ns
t
SIMO inp t data set p time
2.2 V
20
ns
tSU,SI
SIMO input data setup time
3V
15
ns
t
SIMO inp t data hold time
2.2 V
10
ns
tHD,SI
SIMO input data hold time
3V
10
ns
t
SOMI o tp t data alid time
UCLK edgetoSOMIvalid,
2.2 V
75
110
ns
tVALID,SO
SOMI output data valid time
UCLK edge to SOMI valid,
CL =20pF
3V
50
75
ns
NOTE:
f
UCxCLK
=
1
2t
LO∕HI
with
t
LO∕HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master’s parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached master.
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