參數(shù)資料
型號: MSP430F47126IPZR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 47/87頁
文件大?。?/td> 1538K
代理商: MSP430F47126IPZR
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
51
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (SPI slave mode) (see Note 1, Figure 23, and Figure 24)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
tSTE,LEAD
STE lead time
STE low to clock
2.2 V/3 V
50
ns
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V
10
ns
tSTE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
ns
t
SIMO input data setup time
2.2 V
20
ns
tSU,SI
SIMO input data setup time
3V
15
ns
t
SIMO input data hold time
2.2 V
10
ns
tHD,SI
SIMO input data hold time
3V
10
ns
t
SOMI output data valid time (Note 2)
UCLK edgetoSOMIvalid,
2.2 V
75
110
ns
tVALID,SO
SOMI output data valid time (Note 2)
UCLK edge to SOMI valid,
CL =20pF
3V
50
75
ns
t
SOMI output data hold time (Note 3)
C
20 pF
2.2 V
0
ns
tHD,MO
SOMI output data hold time (Note 3)
CL =20pF
3V
0
ns
NOTES: 1.
f
UCxCLK
=
1
2t
LO∕HI
with
t
LO∕HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master’s parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached master.
2. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 23 and Figure 24.
3. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Negative values indicate that the
data on the SOMI output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams
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