參數(shù)資料
型號(hào): MSP430F47187IPZ
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP100
封裝: GREEN, PLASTIC, QFP-100
文件頁(yè)數(shù): 49/87頁(yè)
文件大?。?/td> 1538K
代理商: MSP430F47187IPZ
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
53
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 25)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fUSCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% 10%
fSYSTEM MHz
fSCL
SCL clock frequency
2.2 V/3 V
0
400
kHz
t
Hold time (repeated) START
fSCL 100kHz (standard mode)
2.2 V/3 V
4.0
s
tHD,STA
Hold time (repeated) START
fSCL > 100kHz (fast mode)
2.2 V/3 V
0.6
s
t
Set p time for a repeated START
fSCL 100kHz (standard mode)
2.2 V/3 V
4.7
s
tSU,STA
Setup time for a repeated START
fSCL > 100kHz (fast mode)
2.2 V/3 V
0.6
s
tHD,DAT
Data hold time
2.2 V/3 V
0
ns
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
t
Setup time for STOP
fSCL 100kHz (standard mode)
2.2 V/3 V
4.0
s
tSU,STO
Setup time for STOP
fSCL > 100kHz (fast mode)
2.2 V/3 V
0.6
s
t
Pulse width of spikes suppressed by
2.2 V
50
150
600
ns
tSP
Pulse width of spikes suppressed by
input filter
3V
50
100
600
ns
SDA
SCL
1/fSCL
tHD,DAT
tSU,DAT
tHD,STA
tSU,STA tHD,STA
tSU,STO
tSP
Figure 25. I2C Mode Timing
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