參數(shù)資料
型號(hào): MSP430F5131IRSBT
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC40
封裝: GREEN, PLASTIC, WQFN-40
文件頁(yè)數(shù): 58/102頁(yè)
文件大?。?/td> 1183K
代理商: MSP430F5131IRSBT
MSP430F51x1
MSP430F51x2
SLAS619A
– AUGUST 2010 – REVISED AUGUST 2011
10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1.4 V
≤ (VEREF+ – VEREF-)min ≤ 1.6 V
±1.0
Integral
EI
LSB
linearity error
1.6 V
< (VEREF+ – VEREF-)min ≤ VAVCC
±1.0
Differential
(VEREF+
– VEREF-)min ≤ (VEREF+ – VEREF-),
ED
±1.0
LSB
linearity error
CVEREF+ = 20 pF
(VEREF+
– VEREF-)min ≤ (VEREF+ – VEREF-),
EO
Offset error
Internal impedance of source RS < 100 ,
±1.0
LSB
CVEREF+ = 20 pF
Gain error, external
±1.0
LSB
reference
(VEREF+
– VEREF-)min ≤ (VEREF+ – VEREF-),
CVEREF+ = 20 pF
Gain error, external
EG
±1.5
LSB
reference, buffered
Gain error, internal
See (1)
±1.5%
VREF
reference
Total unadjusted
error, external
(VEREF+
– VEREF-)min ≤ (VEREF+ – VEREF-),
±1.0
±2.0
LSB
buffered and
CVEREF+ = 20 pF
unbuffered reference
ET
Total unadjusted
error, internal
See (1)
±1.5%
VREF
reference
(1)
Dominated by the absolute voltage of the integrated reference voltage.
REF, External Reference (MSP430F51x2 Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Positive external
VEREF+
> VEREF- (2)
1.4
AVCC
V
reference voltage input
Negative external
VEREF-
VEREF+
> VEREF- (3)
0
1.2
V
reference voltage input
VEREF+
Differential external
VEREF+
> VEREF- (4)
1.4
AVCC
V
VEREF-
reference voltage input
1.4 V
≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
2.2 V/3 V
±8.5
±26
A
Conversion rate 200 ksps
I(VEREF+)
Static input current
I(VEREF-)
1.4 V
≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
2.2 V/3 V
±1
A
Conversion rate 20 ksps
Capacitance at
C(VEREF+/-)
See (5)
10
F
VEREF+/- terminal
(1)
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2)
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3)
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4)
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5)
Two decoupling capacitors, 10
F and 100 nF, should be connected to VEREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the MSP430x5xx/MSP430x6xx Family User
's Guide (SLAU208).
Copyright
2010–2011, Texas Instruments Incorporated
59
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