參數(shù)資料
型號: MSP430F5436IPZ
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP100
封裝: GREEN, PLASTIC, LQFP-100
文件頁數(shù): 50/99頁
文件大?。?/td> 985K
代理商: MSP430F5436IPZ
MSP430F543x, MSP430F541x
SLAS612C – AUGUST 2009 – REVISED MARCH 2010
www.ti.com
Wake-up from Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX UNIT
Wake-up time from
tWAKE-UP-
PMMCOREV = SVSMLRRL = 2
LPM2, LPM3, or LPM4
2.2/3.0 V
5
s
FAST
SVSLFP = 1
to active mode(1)
Wake-up time from
tWAKE-UP-
PMMCOREV = SVSMLRRL = 2
LPM2, LPM3 or LPM4 to
2.2/3.0 V
150
s
SLOW
SVSLFP = 0
active mode(2)
(1)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the
MSP430x5xx Family User's Guide (SLAU208).
(2)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
1.8 V/
fTA
Timer_A input clock frequency
External: TACLK
25
MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs.
1.8 V/
tTA,cap
Timer_A capture timing
Minimum pulse width required for
20
ns
3.0 V
capture.
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
1.8 V/
fTB
Timer_B input clock frequency
External: TBCLK
25
MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs.
1.8 V/
tTB,cap
Timer_B capture timing
Minimum pulse width required for
20
ns
3.0 V
capture.
54
Copyright 2009–2010, Texas Instruments Incorporated
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