參數(shù)資料
型號： MSP430F5519IPN
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP80
封裝： GREEN, PLASTIC, LQFP-80
文件頁數(shù)： 67/119頁
文件大?。?/td> 1351K
代理商： MSP430F5519IPN
MSP430F551x
MSP430F552x
SLAS590E
– MARCH 2009 – REVISED APRIL 2011
Schmitt-Trigger Inputs
– General Purpose I/O
(1)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1.8 V
0.80
1.40
VIT+
Positive-going input threshold voltage
V
3 V
1.50
2.10
1.8 V
0.45
1.00
VIT–
Negative-going input threshold voltage
V
3 V
0.75
1.65
1.8 V
0.3
0.85
Vhys
Input voltage hysteresis (VIT+ – VIT–)
V
3 V
0.4
1.0
For pullup: VIN = VSS
RPull
Pullup/pulldown resistor(2)
20
35
50
k
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
5
pF
(1)
Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2)
Also applies to RST pin when pullup/pulldown resistor is enabled.
Inputs
– Ports P1 and P2
(1)
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
t(int)
External interrupt timing(2)
External trigger pulse width to set interrupt flag
2.2 V/3 V
20
ns
(1)
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2)
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
Leakage Current
– General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
Ilkg(Px.x)
High-impedance leakage current
(1) (2)
1.8 V/3 V
-50
50
nA
(1)
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2)
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs
– General Purpose I/O (Full Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
I(OHmax) = –3 mA
(1)
VCC – 0.25
VCC
1.8 V
I(OHmax) = –10 mA
(2)
VCC – 0.60
VCC
VOH
High-level output voltage
V
I(OHmax) = –5 mA
(1)
VCC – 0.25
VCC
3 V
I(OHmax) = –15 mA
(2)
VCC – 0.60
VCC
I(OLmax) = 3 mA
(1)
VSS VSS + 0.25
1.8 V
I(OLmax) = 10 mA
(2)
VSS VSS + 0.60
VOL
Low-level output voltage
V
I(OLmax) = 5 mA
(1)
VSS VSS + 0.25
3 V
I(OLmax) = 15 mA
(2)
VSS VSS + 0.60
(1)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Copyright
2009–2011, Texas Instruments Incorporated
51
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