參數(shù)資料
型號: MSP430F5519IPNR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, RISC MICROCONTROLLER, PQFP80
封裝: GREEN, PLASTIC, LQFP-80
文件頁數(shù): 35/119頁
文件大小: 1351K
代理商: MSP430F5519IPNR
MSP430F551x
MSP430F552x
SLAS590E
– MARCH 2009 – REVISED APRIL 2011
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 8. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User
's
Table 8. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input/TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 9. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User
's Guide (SLAU278.
Table 9. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information memory.
Segment A can be locked separately.
22
Copyright
2009–2011, Texas Instruments Incorporated
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