參數(shù)資料
型號： MSP430F5638IPZR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝： GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 53/101頁
文件大?。?/td> 1073K
代理商： MSP430F5638IPZR
PRODUCTPREVIEW
MSP430F563x
www.ti.com
SLAS650A – JUNE 2010 – REVISED JULY 2010
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1.8 V
11
PMMCOREV = 0
ns
3 V
8
tSTE,LEAD
STE lead time, STE low to clock
2.4 V
7
PMMCOREV = 3
ns
3 V
6
1.8 V
3
PMMCOREV = 0
ns
3 V
3
tSTE,LAG
STE lag time, Last clock to STE high
2.4 V
3
PMMCOREV = 3
ns
3 V
3
1.8 V
66
PMMCOREV = 0
ns
3 V
50
tSTE,ACC
STE access time, STE low to SOMI data out
2.4 V
36
PMMCOREV = 3
ns
3 V
30
1.8 V
30
PMMCOREV = 0
ns
3 V
23
STE disable time, STE high to SOMI high
tSTE,DIS
impedance
2.4 V
16
PMMCOREV = 3
ns
3 V
13
1.8 V
5
PMMCOREV = 0
ns
3 V
5
tSU,SI
SIMO input data setup time
2.4 V
2
PMMCOREV = 3
ns
3 V
2
1.8 V
5
PMMCOREV = 0
ns
3 V
5
tHD,SI
SIMO input data hold time
2.4 V
5
PMMCOREV = 3
ns
3 V
5
UCLK edge to SOMI valid,
1.8 V
76
CL = 20 pF
ns
3 V
60
PMMCOREV = 0
tVALID,SO
SOMI output data valid time(2)
UCLK edge to SOMI valid,
2.4 V
44
CL = 20 pF
ns
3 V
40
PMMCOREV = 3
1.8 V
18
CL = 20 pF
ns
PMMCOREV = 0
3 V
12
tHD,SO
SOMI output data hold time(3)
2.4 V
10
CL = 20 pF
ns
PMMCOREV = 3
3 V
8
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
(2)
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5 and Figure 6.
(3)
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Copyright 2010, Texas Instruments Incorporated
55
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