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參數(shù)資料
| 型號： | MSP430FE4252IPMR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8.4 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | GREEN, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 4/48頁 |
| 文件大小： | 891K |
| 代理商： | MSP430FE4252IPMR |
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MSP430FE42x2
MIXED SIGNAL MICROCONTROLLER
SLAS616 JULY 2008
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
oscillator and system clock
The clock system in the MSP430FE42x2 family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a
high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low
system cost and low power consumption. The FLL+ features a digital frequency-locked loop (FLL) hardware
that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the
watch-crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6
s.
The FLL+ module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports
both supply-voltage supervision (the device is automatically reset) and supply-voltage monitoring (SVM) (the
device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure that the default FLL+ settings are not changed until
VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins).
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.
D Read/write access to port-control registers is supported by all instructions.
NOTE:
Only six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits
for port P2 are implemented.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
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