參數(shù)資料
型號(hào): MSP430FR5721IDA
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 24 MHz, RISC MICROCONTROLLER, PDSO38
封裝: PLASTIC, TSSOP-38
文件頁數(shù): 6/76頁
文件大小: 1059K
代理商: MSP430FR5721IDA
PRODUCTPREVIEW
MSP430FR573x
MSP430FR572x
SLAS639
– APRIL 2011
Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
RH
RG
DA
PW
A
E
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices
without TB2)
P2.2/TB2.2/UCB0CLK/ TB1.0
23
15
25
21
I/O
Clock signal input
– eUSCI_B0 SPI slave mode; Clock signal output –
eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices
without TB1)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices
P3.4/TB1.1/TB2CLK/ SMCLK
24
N/A
26
N/A
I/O
without TB1)
TB2 clock input (not available on devices without TB2 or package options
PW, RGE)
SMCLK output (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.5/TB1.2/CDOUT
25
N/A
27
N/A
I/O
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on devices
without TB1)
Comparator_D output (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on devices
P3.6/TB2.1/TB1CLK
26
N/A
28
N/A
I/O
without TB2)
TB1 clock input (not available on devices without TB1 or package options
PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.7/TB2.2
27
N/A
29
N/A
I/O
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on devices
without TB2 or package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on devices
P1.6/TB1.1/UCB0SIMO/
without TB1)
28
16
30
22
I/O
UCB0SDA/TA0.0
Slave in, master out
– eUSCI_B0 SPI mode
I2C data
– eUSCI_B0 I2C mode
TA0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on devices
P1.7/TB1.2/UCB0SOMI/
without TB1)
29
17
31
23
I/O
UCB0SCL/TA1.0
Slave out, master in
– eUSCI_B0 SPI mode
I2C clock
– eUSCI_B0 I2C mode
TA1 CCR0 capture: CCI0A input, compare: Out0
Regulated core power supply (internal usage only, no external current
VCORE(2)
30
18
32
24
loading)
DVSS
31
19
33
25
Digital ground supply
DVCC
32
20
34
26
Digital power supply
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.7
33
N/A
35
N/A
I/O
(not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options RGE)
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on package
P2.3/TA0.0/UCA1STE/
options RGE)
34
N/A
36
27
I/O
A6/CD10
Slave transmit enable
– eUSCI_A1 SPI mode (not available on devices
without eUSCI_A1)
Analog input A6
– ADC (not available on devices without ADC)
Comparator_D input CD10 (not available on package options RGE)
(2)
VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
14
Copyright
2011, Texas Instruments Incorporated
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