參數(shù)資料
型號: MSP430FR5726IPW
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 24 MHz, RISC MICROCONTROLLER, PDSO28
封裝: PLASTIC, TSSOP-28
文件頁數(shù): 10/76頁
文件大小: 1059K
代理商: MSP430FR5726IPW
PRODUCTPREVIEW
MSP430FR573x
MSP430FR572x
SLAS639
– APRIL 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
SYSTEM
WORD
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
INTERRUPT
ADDRESS
System Reset
Power-Up, Brownout, Supply
SVSLIFG, SVSHIFG
Supervisors
PMMRSTIFG
External Reset RST
WDTIFG
Watchdog Timeout (Watchdog
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
mode)
DBDIFG
Reset
0FFFEh
63, highest
WDT, FRCTL MPU, CS, PMM
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
Password Violation
MPUSEG3IFG
FRAM double bit error detection
PMMPORIFG, PMMBORIFG
MPU segment violation
(SYSRSTIV)(1) (2)
Software POR, BOR
System NMI
VMAIFG
Vacant Memory Access
JMBNIFG, JMBOUTIFG
JTAG Mailbox
ACCTIMIFG
FRAM access time error
ACCVIFG
(Non)maskable
0FFFCh
62
Access violation
SBDIFG, DBDIFG
FRAM single, double bit error
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
detection
MPUSEG3IFG
MPU segment violation
(SYSSNIV)(1)
User NMI
NMIIFG, OFIFG
External NMI
(Non)maskable
0FFFAh
61
(SYSUNIV)(1) (2)
Oscillator Fault
Comparator_D interrupt flags
Comparator_D
Maskable
0FFF8h
60
(CBIV)(1) (3)
TB0
TB0CCR0 CCIFG0 (3)
Maskable
0FFF6h
59
TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2,
TB0
TB0IFG
Maskable
0FFF4h
58
(TB0IV)(1) (3)
Watchdog Timer (Interval Timer
WDTIFG
Maskable
0FFF2h
57
Mode)
UCA0RXIFG, UCA0TXIFG (SPI mode)
UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG,
eUSCI_A0 Receive/Transmit
Maskable
0FFF0h
56
UXA0TXIFG (UART mode)
(UCA0IV)(1) (3)
UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG,
UCB0TXIFG (SPI mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0,
eUSCI_B0 Receive/Transmit
Maskable
0FFEEh
55
UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2,
UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3,
UCB0CNTIFG, UCB0BIT9IFG (I2C mode)
(UCAB0IV)(1) (3)
ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG,
ADC10LOIFG
ADC10_B
Maskable
0FFECh
54
ADC10INIFG, ADC10IFG0
(ADC10IV)(1) (3) (4)
TA0
TA0CCR0 CCIFG0(3)
Maskable
0FFEAh
53
TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2,
TA0
TA0IFG
Maskable
0FFE8h
52
(TA0IV)(1) (3)
(1)
Multiple source flags
(2)
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3)
Interrupt flags are located in the module.
(4)
Only on devices with ADC, otherwise reserved.
18
Copyright
2011, Texas Instruments Incorporated
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