參數(shù)資料
型號(hào)： MSP430G2113IPW20
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁數(shù)： 28/68頁
文件大小： 858K
代理商： MSP430G2113IPW20
SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
MSP430G2x53
MSP430G2x13
SLAS735C
– APRIL 2011 – REVISED AUGUST 2011
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fUSCI
USCI input clock frequency
SMCLK, duty cycle = 50%
± 10%
fSYSTEM
MHz
fSCL
SCL clock frequency
3 V
0
400
kHz
fSCL ≤ 100 kHz
4.0
tHD,STA
Hold time (repeated) START
3 V
s
fSCL > 100 kHz
0.6
fSCL ≤ 100 kHz
4.7
tSU,STA
Setup time for a repeated START
3 V
s
fSCL > 100 kHz
0.6
tHD,DAT
Data hold time
3 V
0
ns
tSU,DAT
Data setup time
3 V
250
ns
tSU,STO
Setup time for STOP
3 V
4.0
s
Pulse width of spikes suppressed by
tSP
3 V
50
100
600
ns
input filter
Figure 20. I2C Mode Timing
Comparator_A+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
I(DD)
(1)
CAON = 1, CARSEL = 0, CAREF = 0
3 V
45
A
I(Refladder/
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
3 V
45
A
RefDiode)
No load at CA0 and CA1
V(IC)
Common
–mode input voltage
CAON = 1
3 V
0
VCC-1
V
PCA0 = 1, CARSEL = 1, CAREF = 1,
V(Ref025)
(Voltage at 0.25 VCC node) / VCC
3 V
0.24
No load at CA0 and CA1
PCA0 = 1, CARSEL = 1, CAREF = 2,
V(Ref050)
(Voltage at 0.5 VCC node) / VCC
3 V
0.48
No load at CA0 and CA1
PCA0 = 1, CARSEL = 1, CAREF = 3,
V(RefVT)
3 V
490
mV
No load at CA0 and CA1, TA = 85
°C
V(offset)
Offset voltage(2)
3 V
±10
mV
Vhys
Input hysteresis
CAON = 1
3 V
0.7
mV
TA = 25°C, Overdrive 10 mV,
120
ns
Without filter: CAF = 0
Response time
t(response)
3 V
(low-high and high-low)
TA = 25°C, Overdrive 10 mV,
1.5
s
With filter: CAF = 1
(1)
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
(2)
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
34
Copyright
2011, Texas Instruments Incorporated
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