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參數(shù)資料
| 型號(hào)： | MT48V4M32LFFC |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 14/61頁 |
| 文件大?。?/td> | 1400K |
| 代理商： | MT48V4M32LFFC |
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14
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x16, x32
MOBILE SDRAM
ADVANCE
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CS# RAS# CAS# WE# DQM
H
X
X
L
H
H
L
L
H
L
H
L
L
H
L
L
H
H
L
L
H
L
L
L
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
DQs
X
X
X
X
Valid
Active
X
X
NOTES
X
H
H
H
L
L
L
H
X
X
X
3
4
4
L/H
8
L/H
8
X
X
X
5
6, 7
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
Op-Code
–
–
X
2
8
8
Active
High-Z
following the Operation section; these tables provide
current state/next state information.
Commands
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0-
7, DQM1 controls DQ8-15, DQM2 controls DQ16-23, and DQM3 controls DQ24-31.
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