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參數(shù)資料
| 型號： | MT5C1009ECA-15/XT |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 15 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 137K |
| 代理商： | MT5C1009ECA-15/XT |
SRAM
MT5C1009
MT5C1009
Rev. 6.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
Austin Semiconductor, Inc.
ACTEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS (GND).
2.
-2V for pulse width < 20ns
3.
I
CC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
tRC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7.
At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE and tHZOE is less than tLZOE.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
+5V
Q
255
30
480
5 pF
+5V
Q
255
480
123
1234
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
---
V
ICCDR1*
0.75
mA
ICCDR2
1.0
mA
Chip Deselect to Data
Retention Time
tCDR
0
---
ns
4
Operation Recovery Time
tR
tRC
ns
4, 11
Data Retention Current
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 2V
CONDITIONS
12345678
123
1234
123456789
123
1234
DATA RETENTION MODE
V
DR > 2V
4.5V
V
DR
t
CDR
t
R
V
IH
V
IL
V
CC
CE1\
* Low Power, -20 device only
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT5C1009ECA-20/883C | 制造商:Micross Components, Inc. 功能描述:SRAM, 1MB - Trays |
| MT5C1009ECA-20/IT | 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
| MT5C1009ECA-20/XT | 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
| MT5C1009ECA-20L/883C | 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
| MT5C1009ECA-20L/IT | 制造商:Micross Components 功能描述:SRAM, 1MB - Trays |
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