參數(shù)資料
型號: MT80C51C-12D
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44
封裝: 1 MM HEIGHT, QFP-44
文件頁數(shù): 165/170頁
文件大?。?/td> 4133K
代理商: MT80C51C-12D
94
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
13.12.4
ADCL
ADC Data Register
When an ADC conversion is complete, the result is found in the ADC register.
Bits 7:0 – ADC7:0: ADC Conversion Result
These bits represent the result from the conversion.
13.12.5
DIDR0
Digital Input Disable Register 0
Bits 7:4 – Res: Reserved Bit
These bits are reserved and will always read zero.
Bits 3:0 – ADC3D..ADC0D: ADC3..0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corre-
sponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the
ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power
consumption in the digital input buffer.
1
0
Timer/Counter 0 Overflow
1
0
1
Timer/Counter 0 Compare Match B
1
0
Pin Change Interrupt 0 Request
1
Timer/Counter 0 Capture Event
Table 13-4.
ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
Bit
765
4321
0
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
Read/Write
RRRR
Initial Value
000
0000
0
Bit
765
432
1
0
ADC3D
ADC2D
ADC1D
ADC0D
DIDR0
Read/Write
R
R/W
Initial Value
0
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