MT8885
Preliminary Information
4-58
Table 2. Actual Frequencies Versus Standard
Requirements
Distortion Calculations
The MT8885 is capable of producing precise tone
bursts with minimal error in frequency (see Table 2).
The internal summing amplifier is followed by a first-
order lowpass switched capacitor filter to minimize
harmonic components and intermodulation products.
The total harmonic distortion for a single tone can be
calculated by using Equation 1, which is the ratio of
the total power of all the extraneous frequencies to
the power of the fundamental frequency expressed
as a percentage.
Equation 1. THD (%) For a Single Tone
The Fourier components of the tone output
correspond to V
2f
.... V
nf
as measured on the output
waveform. The total harmonic distortion for a dual
tone can be calculated by using Equation 2. V
L
and
V
H
correspond to the low group amplitude and high
group amplitude, respectively and V
2
IMD
is the sum
of all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 10.
Equation 2. THD (%) For a Dual Tone
DTMF Clock Circuit
The internal clock circuit is completed with the
additions of a standard television colour burst
crystal. The crystal specification is as follows:
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series Resistance:
Maximum Drive Level:
3.579545 MHz
±
0.1%
Parallel
18pF
150ohms
2mW
e.g.CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8885 devices can be connected as
shown in Figure 11 such that only one crystal is
required. Alternatively, the OSC1 inputs on all
devices can be driven from a CMOS buffer with the
OSC2 outputs left unconnected.
Figure 11 - Common Crystal Connection
Microprocessor Interface
The MT8885 design incorporates an adaptive
interface, which allows it to be connected to various
kinds of microprocessors. Key functions of this
interface include the following:
Continuous activity on DS/RD is not necessary
to update the internal status registers.
Compatible with Motorola and Intel processors.
Determines whether input timing is that of an
Intel or Motorola controller by monitoring
DS/RD, on the CS falling edge.
Differentiates between multiplexed and non-
multiplexed microprocessor buses. Address and
data are latched in accordingly.
Figure 16 shows the timing diagram for the Motorola
microcontrollers. The chip select (CS) input is formed
by NANDing address strobe (AS) and address
decode output. The MT8885 examines the state of
ACTIVE
INPUT
OUTPUT FREQUENCY (Hz)
%ERROR
SPECIFIED
697
770
852
941
1209
1336
1477
1633
ACTUAL
699.1
766.2
847.4
948.0
1215.9
1331.7
1471.9
1645.0
L1
+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73
L2
L3
L4
H1
H2
H3
H4
THD (%) = 100
V
2
fundamental
V
2
2f
+ V
2
3f
+ V
2
4f
+ .... V
2
nf
V
2L
+
V
2H
V
22L
+
V
23L
+ ....
V
2nL
+
V
22H
+
V
23H
+ ..
V
2nH
+
V
2IMD
THD (%) = 100
MT8885
OSC1
OSC2
MT8885
OSC1
OSC2
MT8885
OSC1
OSC2
3.579545 MHz