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| 型號： | MT8930B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 277K |
| 代理商： | MT8930B |
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MSAN-141
Application Note
A-206
the TE will replace the next Fa-bit to be transmitted
with the Q-bit, while the NT will insert the S-channel
into the S-bit.
The multiframing structure consists of five S-Bus
frames which can be identified by the binary
inversion of the Fa and N-bit on the first frame of the
multiframe in the NT to TE frame structure, i.e., Fa =
binary 1 (Space) with N = binary 0 (Mark). This is
activated by setting bit B1 of the NT C-channel
Control Register to a binary one once every five S-
Bus frames. (Note that the TxMFR bit must be set to
binary 0 for four of the five frames in order for the
multiframing of the SNIC to function normally.) Upon
activation of the multiframe signal, the NT can use
the S-bit to forward the S-channel towards the TE.
Upon detection of the multiframe structure, the TE
will replace its transmitted Fa-bit with the transmit
maintenance channel (Q-bit) found in the TE mode
C-channel Control Register. (The TxMCH bit must be
updated every five S-Bus frames to maintain
continuity in the Q-channel.)
Structuring the Q-channel is achieved with a second
level of multiframing using the M-bit found in the NT
to TE frame structure. These bits are defined in
Table 1. Below is an explanation on how the
MT8930B/31B handles multiframing. Note that all
write and read cycles to the device must be done
when the NDA signal is low.
1) Multiframing procedure on the NT side.
Before activation of the S-Bus, the HALF bit in the C-
channel Control Register should be set to ‘1’. In
successive ST-BUS frames, this bit should alternate
between ‘1’ and ‘0’ in every other ST-BUS frame. The
microprocessor must keep track of when HALF is ‘1’
or HALF is ‘0’. This task is needed because the
device makes use of the state of the HALF bit to
transmit the multiframe bits.
To start a multiframe, the TxMFR bit should be set to
‘1’ in the same NDA window when ‘0’ is to be written
to the HALF bit. The device will then set the Fa and N
bits on the line to ‘1’ and ‘0’ respectively. This action
will alert the TE to be ready to receive a multiframe.
The M/S bit in the C-channel control Register should
be used to complete the structuring of the multiframe
as shown in Table 1 by transmitting M and S bits. The
M/S bit transmits the M bit on the S-Bus when HALF
is ‘0’, and the S bit when HALF is ‘1’.
The received Q-channel from the TE is presented in
the RxMCH bit of the C-channel Status Register. It
)
Table 1. Multiframe Structure
should be read in the same NDA window when ‘0’ is
to be written to the HALF bit. Please note that data
written to the TxMFR and M/S bits are latched
internally and will be repeated in every S-Bus frame
unless they are rewritten by the microprocessor. It is
the responsibility of the microprocessor to structure
the multiframe bits (setting and resetting the TxMFR
and M/S bits in corresponding frames) to conform to
the format shown in Table 1.
2) Multiframing procedure on the TE side.
In TE mode, the HALF bit in the C-channel Status
Register is an output. The microprocessor needs
only to monitor the RxMFR bit in the Status Register
for the start of the multiframe. The M and S bits from
the NT will be received in the M/S bit of the status
register. The state of the HALF bit is used to indicate
when the M/S bit presents the M bit or when it
presents the S bit. The TxMCH bit in the C-channel
Control Register is used to transmit the Q-channel
bit to the NT. Note that the TE SNIC will
automatically replace the TxMCH bit with the Fa bit
on the S-Bus frame when the start of a multiframe is
received from the NT (when RxMFR bit is set to ‘1’,
while HALF bit is ‘0’).
2.3
State Activation Machine
CCITT Recommendation I.430 and ANSI T1.605
have defined the activation protocol required on the
S/T interface. This protocol is defined in the form of
information signals termed INFO0 through INFO4.
These signals are defined in Figure 5.
FRAME #
NT
→
TE
F
a
-bit
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
:
NT
→
TE
M-bit
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
:
NT
→
TE
S-bit
SC11
SC21
SC31
SC41
SC51
SC12
SC22
SC32
SC42
SC52
SC13
SC23
SC33
SC43
SC53
SC14
SC24
SC34
SC44
SC54
SC11
SC21
:
TE
→
NT
F
a
-bit
Q1
0
0
0
0
Q2
0
0
0
0
Q3
0
0
0
0
Q4
0
0
0
0
Q1
0
:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
:
相關PDF資料 |
PDF描述 |
|---|---|
| MT8931B | () |
| MT8930C-1 | SWITCH, ON-OFF, CHROM/BLK BTN; Switch function type:SPST Latching; Voltage, contact AC max:125V; Voltage, contact DC max:24V; Temp, op. max:85(degree C); Temp, op. min:-40(degree C); Diameter, panel cut-out:13.6mm; Length / Height, RoHS Compliant: Yes |
| MT8930C | Subscriber Network Interface Circuit(用戶網(wǎng)絡接口電路（提供點到點或點到多點數(shù)字傳送）) |
| MT8930 | CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
| MT8930C | CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8930BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8930BE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8930BP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8930C | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
| MT8930C-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit |
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