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參數(shù)資料
| 型號： | MT8950AC |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
| 中文描述： | 異意法半導(dǎo)體的CMOS總線⑩系列數(shù)據(jù)編解碼器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 223K |
| 代理商： | MT8950AC |
MT8950
ISO-CMOS
6-8
intervals which are multiples of 52μs (depending
upon the input data baud rate).
Functional Description
The functional block diagram of the data codec is
shown in Figure 1. The low speed data to be
encoded is accepted by the NRZ/RZ input circuitry
and relayed to the encoder. The 8 bit encoded word
is transmitted within one channel time period on to
the ST-BUS serial output stream. At the same time
an 8 bit TEM word is loaded into the decoder via the
incoming ST-BUS stream. The low speed data is
regenerated and output by the NRZ/RZ output
circuitry. The data codec can operate in eight
modes. The specific mode of operation is selected
by programming the internal Control Register using
the CSTi serial input.
Transmit Path
The NRZ/RZ input circuitry can be programmed to
accept RZ or NRZ data by asserting the appropriate
level on the DF pin (HIGH=RZ format; LOW=NRZ
format).
In the RZ format, both D
X
1 and D
X
2 are used for the
input data. MARK pulses are received on one line
input and SPACE pulses on the other. The MARK
and SPACE polarities of the input pins are fixed by
the high to low transition of the RxE line. The
input having the last transition before RxE goes low
is selected to be the MARK input. Thus to ensure
correct polarity selection, the data codec should be
receiving MARK pulses before RxE is taken low.
The RxE line must be kept low for the duration of
the call. As indicated before, the Data Codec does
accept violation pulses. The violation pulses can be
input on the MARK or SPACE lines. The time
difference between a violation pulse and an actual
data pulse must be at least 125μs. Since only one
violation pulse is encoded per frame, the minimum
time period between consecutive pulses should be
125μs as illustrated in Figure 4.
In the NRZ format, only one line is required for the
data. This is input at D
X
1 (Pin 9). The second input,
D
X
2, can be used for transmitting secondary control
information. The signal on this input pin is encoded
only when there is no activity on the D
X
1 line, i.e.,
during steady MARK or SPACE condition on the data
line. To ensure proper encoder function, the signal
to the D
X
2 line should be applied after at least 125μs
have elapsed since the last data transition on D
X
1.
The acceptable data format for the D
X
2 input is
illustrated in Figure 5. Each pulse on the line is
encoded as a single transition. The minimum time
period between consecutive pulses should be 125μs.
The encoding of the NRZ/RZ data to the TEM format
is performed by the encoder. The 8 bit TEM words
are transmitted on the outgoing ST-BUS channel via
DSTo. This is a three state output which is enabled
only when both CA and F1i are low (see Figure 11).
Receive Path
The 8 bit word generated by a data codec at a
remote end is shifted in from the incoming ST-BUS
stream via the DSTi input. The word is shifted in at
the same time as the outgoing word is shifted out,
i.e., when both CA and F1i are low as illustrated in
Figure 11. The NRZ/RZ low speed data is
regenerated by the decoder section and output via
D
R
1 and D
R
2.
If the chip is operating in the RZ format, D
R
2
transmits MARK pulses and D
R
1 transmits SPACE
pulses. The format of the output signal is shown in
Figure 4. The width of an output pulse is nominally
35μs and cannot be altered by the user. Violation
pulses will appear on the line on which they were
initially inserted at the remote end.
In the NRZ format D
R
1 outputs the data. The second
output pin D
R
2, transmits the secondary signal. Each
transition in this signal represents one data pulse
encoded by the remote end. An example of the type
of waveform observed is illustrated in Figure 5.
The
synchronizing pulses if the data decoded from DSTi
is idling (i.e., no data transitions) for more than six
clock periods of the Secondary Clock (SCLK). This
Secondary Clock is typically a 600Hz input to the
chip. When the codec is set in the RZ format, these
sync pulses will be either MARK or SPACE violation
pulses, depending on the last data bit transmitted. If
it is operating in the NRZ format, the sync pulses
constitutes a squarewave with high and low
durations of six SCLK periods. This squarewave
appears at the D
R
2 output pin. Synchronization
pulses are transmitted until some activity is detected
by the decoder or the mode of operation is changed
through the Control Register.
NRZ/RZ
output
circuitry
also
transmits
Timing Requirements
The data codec derives all the internal timing from
the 2.048 MHz clock input (C2i) and the two enable
signals F1i and CA. The DSTo output goes from
high impedance to the value of bit 7 of the TEM
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| MT8952BE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
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