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參數(shù)資料
| 型號： | MT8952BP1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, MS-018AB, LCC-28 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 602K |
| 代理商： | MT8952BP1 |
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MT8952B
Data Sheet
12
Zarlink Semiconductor Inc.
TC0-TC3 - Timing Control Bits: In the Internal Timing Mode the transmitter and the receiver sections are enabled
during the times defined by the Timing Control Bits TC0-TC3 (Table 7). This applies only to the ST-BUS channels 0,
2, 3 and 4 carrying the packets or transparent data (channel-1 pertains to C-channel information). The output
CDSTo is put during the remaining time intervals not enabled by these bits.
X : Don’t Care
Table 7 - Timing Control Bits
Interrupt Flag Register (Read)
Reading the Interrupt Flag Register puts the interrupt status bits on the data bus. This register is reset when it is
read and a particular bit will not be set until its particular condition occurs again. The functional details of each bit
are provided in Figure 11.
Figure 11 - Interrupt Flag Register
GA - Go Ahead: This bit when set HIGH, indicates the detection of ‘go ahead’ sequence on the incoming data
stream (CDSTi).
EOPD - End of Packet Detect: A HIGH on this bit confirms the reception of an ‘end of packet’ flag, an abort
sequence or an invalid packet of 24 or more bits on the incoming data stream (CDSTi).
Tx DONE - Transmitter Done: This bit, when HIGH, indicates that the packet transmission is complete and the
Transmit FIFO is empty. The falling edge of TEOP output causes this interrupt status bit to be set HIGH if the FIFO
is empty.
FA - Frame Abort: This bit is set HIGH to indicate that a frame abort has been detected on the incoming data
stream.
Tx 4/19 FULL - Transmit FIFO 4/19 full: This bit if set HIGH, indicates that the transmit FIFO has only 4 bytes
remaining in it and another 15 bytes could be loaded. This bit has significance only when the transmit FIFO is being
depleted and not when it is getting loaded.
Tx URUN - Transmit FIFO underrun: This bit when HIGH, identifies that the transmit FIFO is empty without the
Protocol Controller being given the ‘end of packet’ indication. This indicates that the transmit FIFO has underrun
and the Protocol Controller will transmit an abort sequence automatically. Tx DONE will be set 8 bit times after Tx
URUN is set.
Timing Control Bits
ST-BUS
Channel
Number
Bits
/Frame
TC3
TC2
TC1
TC0
X
000
0
1
X
001
0
2
0
010
0
6
1
010
0
7
X
011
2
8
X
100
3
8
X
101
4
8
X
1
0
2 and 3
16
X
1
2, 3 and 4
24
D7
D6
D5
D4
D3
D2
D1
D0
GA
EOPD
Tx
DONE
FA
Tx
4/19
FULL
Tx
URUN
Rx
15/19
FULL
Rx
OFLW
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