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參數(shù)資料
| 型號(hào)： | MT90210AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Rate Parallel Access Circuit |
| 中文描述： | 多速率電路并行訪問(wèn) |
| 文件頁(yè)數(shù)： | 1/27頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | MT90210AL |
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MT90210
Multi-Rate Parallel Access Circuit
Preliminary Information
Features
Parallel-to-serial and serial-to-parallel
conversion of up to 1536 full duplex channels or
3072 time-slots
Serial port data rates selectable between 2.048,
4.096 or 8.192 Mb/s
Provides a mechanism for a double buffer
function to be implemented in external memory
24 serial I/O lines programmable in different
modes: 12 in/12 out at 8.192 Mb/s (1536 full
duplex channels) or 24 bidirectional line modes
for 2.048 and 4.096 Mb/s
Provides a bidirectional 8-bit parallel port
operating at 16.384 or 32.768 MByte/s for direct
interface to external memory (dual port)
Provides an external 13-bit output address bus
for direct connection with an 8K-position dual
port memory
JTAG boundary scan
Applications
Fast access to ST-BUS, SCSA, MVIP, and
H-MVIP serial backplanes
Voice processing cards for Computer Telephony
Integration (CTI)
Video and teleconferencing bridge cards
Fast DSP access to serial TDM buses
Description
The MT90210 is a 100-pin device used to interface a
parallel bidirectional 8 bit bus to 24 time division
multiplexed (TDM) serial streams. The device is
configured to perform simultaneous parallel-to-serial
and serial-to-parallel conversion with the capability
of handling up to 3072 channels, 1536 on the
transmit and 1536 on the receive direction.
Depending on the operation mode selected at the
mode pins, the individual 64 Kb/s channels on the
serial links may be configured as inputs or outputs.
The data on the parallel bus is in a format suitable for
interfacing with a dual-port RAM. Depending on the
data rate selected by the MD0-MD2 input pins, serial
data is clocked in and out on the serial streams at
either 2.048, 4.096 or 8.192 Mb/s.
DS5026
ISSUE 2
August 1998
Ordering Information
MT90210AL
100 Pin PQFP
-40 to +85
°
C
Figure 1 - Functional Block Diagram
S0
Shift
Registers
Address
Read
Counter
Mode Control
P0
P7
WBC
OEser
External Memory
Access Control
C16+
F0i
PCLK
MD0
MD1
Boundary
Scan Test
T
Generator
S23
MUX
Write
Counter
MD2
HC4
C16-
PLLVDD
PLLVSS
LP1,LP2
PLLAGND
CKout
RST
RDin
Strobe
SCLK
T
T
T
T
Timing
Generation
PLL
RBC R/W1 R/W2
Analog
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| MT9041A | () |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT90220 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Octal IMA/UNI PHY Device |
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
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