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參數(shù)資料
| 型號(hào)： | MT90502 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道AAL2的特區(qū)（多通道自動(dòng)柜員機(jī)AAL2的分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 70K |
| 代理商： | MT90502 |
MT90502
Preliminary Information
4
Pin Description
EPBGA Pin
Name
Description (see notes 1-8)
CPU Bus Interface Pins
AC3
mclk_src
cpu_mode[3:0] CPU Interface Mode Select (4 bits). The CPU Interface Mode Select bits must be
hardwired.
cpu_a[14:0]
CPU Address bus.
CPU Clock.
F25, F23,
J24, J23
AA3, AA4,
Y1, Y2, Y3,
Y4, W1, W2,
W3, W4, V1,
V2, V3, V4,
U1
T2
T1
U4
T4
cpu_wr_rw
cpu_rd_ds
cpu_ale
cpu_a_das
Intel Write & Motorola Read/Write
Intel Read & Motorola Data Strobe
Address Latch Enable
Direct Access Select. ‘1’ selects the direct address space. ‘0’ selects the
indirection registers contained in the CPU interface. This pin can be connected to
the MSB of an address bus but does not behave as an address pin.
CPU chip select
CPU Data bus
U3
cpu_cs
cpu_d[15:0]
T3, R1, R2,
R3, R4, P1,
P2, P3, P4,
N1, N2, N3,
N4, M1, M2,
M3
U2
AC2
AC1
cpu_rdy_ndtack Intel Ready & Motorola Data Ack.
interrupt1
Interrupt 1 (configurable polarity)
interrupt2
Interrupt 2 (configurable polarity)
UTOPIA Interface Pins
C21
A19
D21
D12
D14
A13
txa_led
rxa_led
rxa_alarm
txa_clk
txa_soc
1. txa_enb
2. txa_clav
1. txa_clav
2. txa_enb
txa_d[7:0]
UTOPIA port A TX LED
UTOPIA port A RX LED
UTOPIA port A PHY alarm
UTOPIA port A TX clock
UTOPIA port A TX Start of Cell
1. UTOPIA port A TX Enable (in ATM)
2. UTOPIA port A TX Cell Available (in PHY)
1. UTOPIA port A TX Cell Available (in ATM)
2. UTOPIA port A TX Enable (in PHY)
UTOPIA port A TX Data bus
B13
C15, B15,
A15, C14,
B14, A14,
D13, C13
D15
A9
C12
B9
txa_prty
rxa_clk
rxa_soc
1. rxa_enb
2. rxa_clav
UTOPIA port A TX Parity
UTOPIA port A RX clock
UTOPIA port A RX Start of Cell
1. UTOPIA port A RX Enable (in ATM)
2. UTOPIA port A RX Cell Available (in PHY)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9074 | T1/E1/J1 Single Chip Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
| MT90503AG | 制造商:Microsemi Corporation 功能描述: |
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
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