
MT9072
Data Sheet
89
Zarlink Semiconductor Inc.
14.0 Maintenance and Alarms
14.1 T1 Maintenance and Alarms
14.1.1 T1 Error Insertion
Six types of error conditions can be inserted into the transmit DS1 data stream through control bits, which are
located in address Y03 -Transmit Error Control Word. These error events include bipolar violation errors (BPVE),
CRC-6 errors (CRCE), Ft errors (FTE), Fs errors (FSE), payload errors (PERR) and a loss of signal condition
(LOSE). If LOSE is one the selected framer transmits an all zeros signal (no pulses) and zero code suppression is
overridden. If LOSE bit is zero, data is transmitted normally.
14.1.2 T1 Per Timeslot Control
There are 24 per timeslot control registers occupying a total of 24 unique addresses (Y90-YA7). Each register
controls a transmit timeslot and the equivalent channel data on DSTo. For example, register address Y90 of the first
per timeslot control register contains program control for transmit timeslot 0 and DSTo channel 0.
14.1.3 T1 Per Timeslot Looping
Any channel or combination of channels may be looped from transmit (sourced from DSTi) to receive (output on
DSTo) ST-BUS channels. When bit 4 (LTSL) in the Per Timeslot Control Word(Y90-YA7) is set the data from the
equivalent transmit channel is looped back onto the equivalent receive timeslot.
Any channel or combination of channels may be looped from receive (sourced from the line data) to transmit
(output onto the line) channels. When bit 5 (RTSL) in the Per Timeslot Control Word is set the data from the
equivalent receive timeslot is looped back onto the equivalent transmit timeslot.
Counter
Source Interrupt Status Bits
1 Second Latch
Description
Bits
Address
Bit
Indication Overflow
Description
Bit
Address
PRBS Error Counter
PEC7-0
Y15
PEI
PEO
NA
NA
NA
PRBS CRC-4 MF
Counter
PCC7-0
Y15
CALN
NA
PCO
NA
NA
NA
Loss of Sync
Counter
SLC7-0
Y16
BSYNC
BSYNC
SLO
NA
NA
NA
E-bit Error Counter
EEC15-0
Y17
REB1
REB2
EEI
EEO
E-bit Error
Count Latch
EEL15-0
Y28
BPV Error Counter
VEC15-0
Y18
VEI
VEO
BPV Error
Count Latch
VEL15-0
Y29
CRC-4 Error
Counter
CEC15-0
Y19
CRCS1
CRCS2
CEI
CEO
CRC-4 Error
Count Latch
CEL15-0
Y2A
FAS Bit Error
Counter
BEC7-0
Y1A
BEI
BEO
FAS Bit Error
Count Latch
BEL7-0
Y2B
FAS Error Counter
FEC7-0
Y1A
FEI
FEO
FAS Error
Count Latch
FEL7-0
Y2B
Table 43 - Error Counter and Event Dependency (E1)