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參數(shù)資料
| 型號： | MT9075A |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | E1 Single Chip Transceiver |
| 中文描述： | 素E1單芯片收發(fā)器 |
| 文件頁數(shù)： | 61/78頁 |
| 文件大?。?/td> | 1008K |
| 代理商： | MT9075A |
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Preliminary Information
MT9075A
4-189
Table 91 - HDLC Test Control Register
(Pages 0BH & 0CH, Address 1BH) (continued)
Bit
Name
Functional Description
7 - 0
Crc7 - 0
The LSB byte of the CRC received
from the transmitter. These bits are
as the transmitter sent them; that is,
most
significant
inverted. This register is updated at
the end of each received packet and
therefore should be read when end
of packet is detected.
bit
first
and
Table 89 - Receive CRC LSB Register
(Pages 0BH & 0CH, Address 19H)
Bit
Name
Functional Description
7 - 0
Cnt7 - 0
The
Register.
It is used to indicate the
length of the packet about to be
transmitted. When this register
reaches the count of one, the next
write to the Tx FIFO will be tagged
as an end of packet byte. The
counter decrements at the end of
the write to the Tx FIFO. If the Cycle
bit of Control Register 2 is set high,
the counter will cycle through the
programmed value continuously.
Transmit
Byte
Count
Table 90 - Transmit Byte Count register
(Pages B & C, Address 1AH)
Bit
Name
Functional Description
7
HRST
HDLC Reset.
When this bit is set to
one, the HDLC will be reset. This is
similar to RESET being applied, the
only difference being that this bit will
not be reset automatically. This bit
can only be reset by writing a zero
twice to this location or applying
RESET.
Bit
Name
Functional Description
6
RTloop
RT Loopback.
When this bit is set
to one, receive to transmit HDLC
loopback will be activated. Receive
data, including end of packet
indication, but not including flags or
CRC, will be written to the TX FIFO
as well as the RX FIFO. When the
transmitter is enabled, this data will
be transmitted as though written by
the microprocessor. Both good and
bad packets will be looped back.
Receive to transmit loopback may
also be accomplished by reading
the
RX
FIFO
microprocessor and writing these
bytes, with appropriate tags, into the
TX FIFO.
using
the
5
RSV
Reserved; must be set to 0 for
normal operation.
4
RSV
Reserved; must be set to 0 for
normal operation.
3
RSV
Reserved; must be set to 0 for
normal operation.
2
Ftst
FIFO Test.
This bit when set to one
allows the writing to the RX FIFO
and reading of the TX FIFO through
the microprocessor to allow more
efficient testing of the FIFO status/
interrupt functionality. This is done
by making a TX FIFO write become
a RX FIFO write and a RX FIFO
read become a TX FIFO read. In
addition, EOP/FA and RQ8/RQ9 are
re-defined to be accessible (i.e. RX
write causes EOP/FA to go to RX
fifo input; TX read looks at output of
TX FIFO through RQ8/RQ9 bits).
1
RSV
Reserved; must be set to 0 for
normal operation.
0
Hloop
TR Loopback.
When high, transmit
to receive HDLC loopback will be
activated. The packetized transmit
data will be looped back to the
receive input. RxEN and TxEN bits
must also be enabled.
Table 91 - HDLC Test Control Register
(Pages 0BH & 0CH, Address 1BH)
相關PDF資料 |
PDF描述 |
|---|---|
| MT9075AL | E1 Single Chip Transceiver |
| MT9075AP | E1 Single Chip Transceiver |
| MT9075BL | E1 Single Chip Transceiver |
| MT9075BP | E1 Single Chip Transceiver |
| MT9075B-1 | E1 Single Chip Transceiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9075AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:E1 Single Chip Transceiver |
| MT9075B-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075BL | 制造商:Microsemi Corporation 功能描述:FRAMER E1 5V 100MQFP - Trays |
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