參數(shù)資料
型號(hào): MT9075B
廠商: Mitel Networks Corporation
英文描述: E1 Single Chip Transceiver(E1單片收發(fā)器)
中文描述: 素E1單芯片收發(fā)器(素E1單片收發(fā)器)
文件頁數(shù): 45/82頁
文件大小: 275K
代理商: MT9075B
Preliminary Information
MT9075B
45
Bit
Name
Functional Description
7 - 4
RMA1-4
Receive Multiframe Alignment
Bits One to Four.
These bits are
received on the PCM 30 2048 kbit/
sec. link in bit positions one to four
of time slot 16 of frame zero of
every signalling multiframe. These
bit should be 0000 for proper
signalling multiframe alignment.
3
X1
Receive Spare Bit X1.
This bit is
received on the PCM 30 2048 kbit/
sec. link in bit position five of time
slot 16 of frame zero of every
signalling multiframe.
2
Y
Receive Y-bit.
This bit is received
on the PCM 30 2048 kbit/sec. link in
bit position six of time slot 16 of
frame zero of every signalling
multiframe. The Y bit may indicate
loss of multiframe alignment at the
remote end (1 -loss of multiframe
alignment; 0 - multiframe alignment
acquired).
1 - 0
X2, X3
Receive Spare Bits X2 and X3.
These bits are received on the PCM
30 2048 kbit/sec. link in bit positions
seven and eight respectively, of
time slot 16 of frame zero of every
signalling multiframe.
Table 41 - Receive Multiframe Alignment Signal
(Page 03H, Address 14H)
Bit
Name
Functional Description
7
RSLIP
Receive Slip.
A change of state
(i.e., 1-to-0 or 0-to-1) indicates that
a receive controlled frame slip has
occurred.
6
RSLPD
Receive Slip Direction.
If one,
indicates that the last received
frame slip resulted in a repeated
frame, i.e., system clock is faster
than
network
indicates that the last received
frame slip resulted in a lost frame,
i.e., system clock is slower than
network clock. Updated on an
RSLIP occurrence basis.
clock.
If
zero,
5
AUXP
Auxiliary Pattern.
This bit will go
high when a continuous 101010...
bit stream (Auxiliary Pattern) is
received on the PCM 30 link for a
period of at least 512 bits. If zero,
auxiliary pattern is not being
received. This pattern will be
decoded in the presence of a bit
error rate of as much as 10
-3
.
4
CEFS
Consecutively
Alignment Signal.
This bit goes
high when the last two frame
alignment signals were received in
error. This bit will be low when at
least one of the last two frame
alignment signals is without error.
Errored
Frame
3-0
RxEBC
11-8
Receive Eighth Bit Count.
The
four most significant bit of a counter
that indicates the number of one
eighth bit times there are between
the ST-BUS frame pulse and
receive frame pulse (RxFP).
Table 42 - Most Significant Phase Status Word
(Page 03H, Address 15H)
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