參數(shù)資料
型號(hào)： MT9161B
廠商： Mitel Networks Corporation
元件分類： Codec
英文描述： ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)
中文描述： ISO2 - 5伏的CMOS多精選編解碼器（MFC）中
文件頁數(shù)： 2/30頁
文件大?。?/td> 154K
代理商： MT9161B
MT9160B/61B
Advance Information
80
Figure 2 - Pin Connections
Pin Description
Pin #
20 Pin
Pin #
24 Pin
Name
Description
1
1
V
Bias
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1
μ
F capacitor to V
SSA,
Connect 1
μ
F capacitor to Vref.
Reference Voltage for Codec (Output).
Nominally [(V
DD
/2)-1.9] volts. Used
internally. Connect 0.1
μ
F capacitor to V
SSA,
Connect 1
μ
F capacitor to VBias.
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
Resets internal state of device.
2
2
V
Ref
3
4
PWRST
4
5
IC
Internal Connection.
Tie externally to V
SSD
for normal operation.
A/
μ
- When internal control bit DEn = 0 this CMOS level compatible input pin
governs the companding law used by the filter/Codec;
μ
-Law when tied to V
SSD
and
A-Law when tied to V
DD
. Logically OR’ed with A/
μ
register bit.
IRQ
- When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
5
6
A/
μ
/IRQ
6
7
V
SSD
CS
Digital Ground.
Nominally 0 volts.
7
8
Chip Select (Input).
This input signal is used to select the device for microport
data transfers. Active low. CMOS level compatible.
8
10
SCLK
Serial Port Synchronous Clock (Input).
Data clock for microport. CMOS level
compatible.
9
11
DATA 1
Bidirectional Serial Data.
Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.
10
12
DATA 2
Serial Data Receive.
In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
11
13
D
out
Data Output.
A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.
12
14
D
in
Data Input.
A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
24 PIN PDIP
M -
VSSA
NC
M +
VBias
VRef
NC
PWRST
IC
VSSD
SCLK
DATA1
DATA2
Din
Dout
HSPKR +
HSPKR -
VDD
CLOCKin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
A/
μ
/IRQ
CS
NC
STB/F0i
NC
M -
VSSA
HSPKR +
HSPKR -
VDD
CLOCKin
M +
VBias
VRef
PWRST
IC
VSSD
SCLK
DATA1
DATA2
Din
Dout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
A/
μ
/IRQ
CS
STB/F0i
20 PIN SOIC/SSOP
M -
VSSA
NC
M +
VBias
VRef
NC
PWRST
IC
VSSD
CS
NC
SCLK
DATA1
DATA2
Din
Dout
HSPKR +
HSPKR -
VDD
CLOCKin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
A/
μ
/IRQ
STB/F0i
STBd/FOod
24 PIN PDIP/SOIC/SSOP
MT9160BS/BN
MT9160BE
MT9161BE/BS/BN
相關(guān)PDF資料
PDF描述
MT9161BE ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)
MT9161BN ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)
MT9161BS ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)
MT9160B 5 Volt Multi-Featured Codec (MFC)(5V 多特性編解碼器)
MT9161B 5 Volt Multi-Featured Codec (MFC)(5V 多特性編解碼器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9161BE 制造商:Microsemi Corporation 功能描述:MULTI-FEATURED CODEC 24SOIC W - Rail/Tube
MT9161BN 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)
MT9161BS 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:5 Volt Multi-Featured Codec (MFC)
MT9162 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:5 Volt Single Rail Codec
MT9162AE 制造商:Microsemi Corporation 功能描述:CODEC 20PDIP - Rail/Tube
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