- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383645 > MT9161BN (Mitel Networks Corporation) ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) PDF資料下載
參數(shù)資料
| 型號(hào)： | MT9161BN |
| 廠商： | Mitel Networks Corporation |
| 元件分類(lèi)： | Codec |
| 英文描述： | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| 中文描述： | ISO2 - 5伏的CMOS多精選編解碼器（MFC）中 |
| 文件頁(yè)數(shù)： | 6/30頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | MT9161BN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)
MT9160B/61B
Advance Information
84
Motorola/National operation. Refer to the relative
timing diagrams of Figures 5 and 6.
Receive data is sampled on the rising edge of SCLK
while transmit data is made available concurrent with
the falling edge of SCLK.
Flexible Digital Interface
A serial link is required to transport data between the
MT9160B/61B and an external digital transmission
device. The MT9160B/61B utilizes the ST-BUS
architecture defined by Mitel Semiconductor but also
Figure 4 - Serial Port Relative Timing for Intel Mode 0
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
X
X
A
2
A
1
A
0
R/W
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Delays due to internal processor timing which are transparent.
The MT9160:-latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
y
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
y
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
D
7
D
0
X
X
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
y
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
R/W
X
A
1
A
0
X
D
7
D
0
Delays due to internal processor timing which are transparent.
The MT9160:-latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
y
X
X
A
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9161BS | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9160B | 5 Volt Multi-Featured Codec (MFC)(5V 多特性編解碼器) |
| MT9161B | 5 Volt Multi-Featured Codec (MFC)(5V 多特性編解碼器) |
| MT9162 | ISO2-CMOS 5 Volt Single Rail Codec |
| MT9171 | Digital Subscriber Interface Circuit with RxSB(數(shù)字用戶接口電路（帶接收同步位）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9161BS | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:5 Volt Multi-Featured Codec (MFC) |
| MT9162 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:5 Volt Single Rail Codec |
| MT9162AE | 制造商:Microsemi Corporation 功能描述:CODEC 20PDIP - Rail/Tube |
| MT9162AN | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:5 Volt Single Rail Codec |
| MT9162AN1 | 制造商:Microsemi Corporation 功能描述:CODEC A/ULAW 5V SSOP 制造商:Microsemi Corporation 功能描述:CODEC 20SSOP - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CODEC MFC 5V 20SSOP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。