參數(shù)資料
型號(hào): MT9315
廠(chǎng)商: Zarlink Semiconductor Inc.
英文描述: CMOS Acoustic Echo Canceller
中文描述: 聲學(xué)回聲消除器的CMOS
文件頁(yè)數(shù): 14/30頁(yè)
文件大?。?/td> 361K
代理商: MT9315
Advance Information
MT9315
13
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
*DC Electrical Characteristics are over recommended temperature and supply voltage.
Timing is over recommended temperature and power supply voltages.
11
Input capacitance
C
i
8
pF
12
PWRDN
Positive Threshold Voltage
Hysteresis
Negative Threshold Voltage
V+
V
H
V-
0.75
V
DD
1.0
0.25
V
DD
V
V
V
AC Electrical Characteristics
- Serial Data Interfaces -
Voltages are with respect to ground (V
SS
) unless
otherwise stated
Characteristics
Sym
Min
Typ
Max
Units
Test Notes
1
MCLK Clock High
t
MCH
t
MCL
f
CLK
t
BCH,
t
C4H
t
BLL,
t
C4L
t
BCP
t
SD
20
ns
2
MCLK Clock Low
20
ns
3
MCLK Frequency
19.15
20.5
MHz
4
BCLK/C4i Clock High
90
ns
5
BCLK/C4i Clock Low
90
ns
6
BCLK/C4i Period
240
7900
ns
7
SSI Enable Strobe to Data Delay
(first bit)
80
ns
C
L
=150pF
8
SSI Data Output Delay (excluding
first bit)
t
DD
80
ns
C
L
=150pF
9
SSI Output Active to High
Impedance
t
AHZ
80
ns
C
L
=150pF
10
SSI Enable Strobe Signal Setup
t
SSS
10
t
BCP
-15
ns
11
SSI Enable Strobe Signal Hold
t
SSH
15
t
BCP
-10
ns
12
SSI Data Input Setup
t
DIS
t
DIH
t
F0iS
t
F0iH
t
DSD
t
ASHZ
10
ns
13
SSI Data Input Hold
15
ns
14
F0i Setup
20
150
ns
15
F0i Hold
20
150
ns
16
ST-BUS Data Output delay
80
ns
C
L
=150pF
C
L
=150pF
17
ST-BUS Output Active to High
Impedance
80
ns
18
ST-BUS Data Input Hold time
t
DSH
t
DSS
20
ns
19
ST-BUS Data Input Setup time
20
ns
DC Electrical Characteristics*
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Conditions/Notes
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參數(shù)描述
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