參數(shù)資料
型號(hào): MT93L04
廠商: Zarlink Semiconductor Inc.
英文描述: 128-Channel Voice Echo Canceller
中文描述: 128頻道語(yǔ)音回聲消除器
文件頁(yè)數(shù): 28/56頁(yè)
文件大?。?/td> 903K
代理商: MT93L04
MT93L04
Data Sheet
28
Zarlink Semiconductor Inc.
Figure 6 - Device Configuration
Table 1 - Quiet PCM Code Assignment
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back -to -Back configurations, MuteR and MuteS bits of Echo Canceller B must always
be “0”. Refer to Figure 4 and to Control Register 2 for bit description.
Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125
μ
s) in order to properly clear the filter.
Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
LINEAR
16 bits
2’s complement
SIGN/
MAGNITUDE
μ
-Law
A-Law
CCITT (G.711)
μ
-Law
A-Law
+Zero
(quiet code)
0000h
80h
FFh
D5h
Rin
Rout
Sout
Sin
echo
path A
Optional -12dB pad
echo
path B
+
-
channel A
channel A
+
-
channel B
channel B
E.C.A
E.C.B
a) Normal Configuration (64ms)
Adaptive
Filter (64ms)
Adaptive
Filter (64ms)
Optional -12dB pad
PORT1
PORT2
+
-
channel A
channel A
E.C.A
Sin
Sout
Rout
Rin
b) Extended Delay Configuration (128ms)
echo
path A
Adaptive Filter
(128 ms)
Optional -12dB pad
PORT1
PORT2
+
E.C.A
Sin
Sout
Rout
Rin
c) Back-to-Back Configuration (64ms)
Optional -12dB pad
E.C.B
+
-
echo
path
echo
path
Adaptive
Filter (64ms)
Adaptive
Filter (64ms)
Optional -12dB pad
PORT1
PORT2
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MT93L04A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller
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