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參數(shù)資料
| 型號： | MTA81010-LPI/SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 21/76頁 |
| 文件大?。?/td> | 745K |
| 代理商： | MTA81010-LPI/SO |
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MTA81010
DS39005D-page 28
1995 Microchip Technology Inc.
CALL
Subroutine Call
Syntax:
CALL k
Encoding:
Words:
1
Cycles:
2
Operation:
PC + 1
→ TOS; k → PC<7:0>,
'0'
→ PC<8>, PA2, PA1, PA0 →
PC<11:9>;
Status bits:
None
Description:
Subroutine call. First, return address
(PC + 1) is pushed into the stack. The
8-bit value is loaded into PC bits <7:0>.
PC bit9 is cleared. PC <2:0> bits are
loaded into PC <11:9>. CALL is a
2-cycle instruction.
CLRF
Clear f and Clear d
Syntax:
CLRF f,d
Encoding:
Words:
1
Cycles:
1
Operation:
00h
→ f, 00h → d
Status bits:
None
Description:
The contents of register “f” are set to 0.
If “d” is 0 the contents of both data
memory location “f” and W register are
set to 0. If “d” is 1 the only contents of
register “f” are set to 0.
CLRW
Clear W Register
Syntax:
CLRW
Encoding:
Words:
1
Cycles:
1
Operation:
00h
→ W
Status bits:
Z
Description:
W registered is cleared. Zero bit (Z) is
set.
CLRWDT
Clear Watchdog Timer
Syntax:
CLRWDT
Encoding:
Words:
1
Cycles:
1
Operation:
00h
→ WDT, 0 → WDT prescaler,
Status bits:
1
→ TO, 1 → PD
Description:
CLRWDT
instruction
resets
the
Watchdog timer. It also resets the
prescaler of the WDT. Status bits TO
and PD are set.
1001 kkkk
kkkk
0000
011f
ffff
0000 0100 0000
0000 0000 0100
COMF
Complement f
Syntax:
COMF f,d
Encoding:
Words:
1
Cycles:
1
Operation:
f
→ d
Status bits:
Z
Description:
The
contents
of
register
“f”
are
complemented. If “d” is 0 the result is
stored in W. If “d” is 1 the result is
stored back in register “f”.
DECF
Decrement f
Syntax:
DECF f,d
Encoding:
Words:
1
Cycles:
1
Operation:
(f-1)
→ d
Status bits:
C, DC, Z
Description:
Decrement register “f”. If “d” is 0 the
result is stored in the W register. If “d”
is 1 the result is stored back in register
“f”.
DECFSZ
Decrement f, skip if 0
Syntax:
DECFSZ f,d
Encoding:
Words:
1
Cycles:
1 (2)
Operation:
(f - 1)
→ d; skip if result = 0
Status bits:
None
Description:
The
contents
of
register
“f”
are
decremented. If “d” is 0 the result is
placed in the W register. If “d” is 1 the
result is placed back in register “f”. If
the result is 0 the next instruction is
skipped.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOP is executed instead making it a
2-cycle instruction.
0010
01df
ffff
0010
11df
ffff
0010
11df
ffff
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