- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68019 > MTA85412S-04I/SS 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20 PDF資料下載
參數(shù)資料
| 型號： | MTA85412S-04I/SS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 45/72頁 |
| 文件大小： | 760K |
| 代理商： | MTA85412S-04I/SS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
1995 Microchip Technology Inc.
DS40115C-page 5
MTA85XXX
2.0
ARCHITECTURAL
DESCRIPTION
2.1
Harvard Architecture
The MTA85XXX microcontrollers are low-power, high-
speed, full static CMOS devices containing EEPROM,
EPROM, RAM, I/O and a central processing unit in a
single package.
The architecture is based on a register file concept with
separate bus and memories for data and instructions
(Harvard architecture). The data bus and memory
(RAM) are 8-bits wide while the program bus and
program memory (EPROM) have a width of 12-bits.
This concept allows a simple yet powerful instruction
set designed to emphasize bit, byte and register
operations
under
high
speed
with
overlapping
instruction fetch and execution cycles. That means
that, while one instruction is executed, the following
instruction is already being read from the program
memory. A block diagram of the MTA85XXX is given in
Figure 2-1.
2.2
Clocking Scheme/Instruction Cycle
The clock input (from pin OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, PC is
incremented every Q1, instruction is fetched from
program memory and latched into instruction register in
Q4. It is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 2-2.
FIGURE 2-1:
MTA85XXX SERIES BLOCK DIAGRAM
MTA85X0X devices have PIC16C5XA VDD tied to EEPROM VDD.
MTA85X1X devices have PIC16C5XA RB7 tied to EEPROM VDD.
Page
Latches
EEPROM
Array
HV
Generator
Memory
Control
Logic
Sense
AMP R/W
Control
I/O
Control
Logic
YDEC
XDEC
SDA
SCL
VDD
VSS
1
RB7
VDD
VSS
WDT
Time Out
8
STACK1
STACK2
EPROM
512 X 12 To
2048 X 12
Instruction
Register
Instruction
Decoder
Watchdog
Timer
Configuration WORD
Oscillator/
Timing &
Control
General
Purpose
Register
File
(SRAM)
24-72
Bytes
WDT/TMR0
Prescaler
Option
Reg.
“OPTION”
“SLEEP”
“Code
Protect”
“OSC
Select”
Direct
TMR0
From W
“TRIS 5”
“TRIS 6”
“TRIS 7”
FSR
TRISA PORTA
From W
T0CKI
PIN
9-11
12
8
W
4
Data
8
ALU
STATUS
From W
CLKOUT
8
9
6
5
5-7
OSC1
OSC2
MCLR
Li
te
ra
ls
PC
“Disable"
2
RA3:RA0
RB7:RB0
RC7:RC0
(28-Pin
Devices Only)
Direct RAM
Address
TRISB PORTB
TRISC PORTC
PIC16C5XA Portion
Block Diagram
EEPROM Portion
Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTA85802S-10I/SS | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| MTA85811-04I/SS | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20 |
| MTA85802-10I/SS | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| MTA85801-10I/SS | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| MTA85812-10I/SS | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTA8808 | 制造商:Pulse Electronics Corporation 功能描述: |
| MTA8ATF1G64AZ-2G3B1 | 功能描述:Memory Module DDR4 SDRAM 8GB 2400MT/s 288-UDIMM 制造商:micron technology inc. 系列:- 零件狀態(tài):在售 存儲器類型:DDR4 SDRAM 存儲容量:8GB 速度:2400MT/s 封裝/外殼:288-UDIMM 標(biāo)準(zhǔn)包裝:1 |
| MTA8ATF1G64HZ-2G3B1 | 功能描述:Memory Module DDR4 SDRAM 8GB 2400MT/s 260-SODIMM 制造商:micron technology inc. 系列:- 零件狀態(tài):在售 存儲器類型:DDR4 SDRAM 存儲容量:8GB 速度:2400MT/s 封裝/外殼:260-SODIMM 標(biāo)準(zhǔn)包裝:1 |
| MTA8D50 | 制造商:Mallory Sonalert Products Inc 功能描述:Molded Tubular Aluminum Electrolytic Axial Leads Capacitor - 8uF 50dcV -10+100% |
| MTA90A | 制造商:LIUJING 制造商全稱:LIUJING 功能描述:可控硅(晶閘管) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。