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參數(shù)資料
| 型號： | MTA85801S-10I/SS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 6/72頁 |
| 文件大?。?/td> | 760K |
| 代理商： | MTA85801S-10I/SS |
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MTA85XXX
DS40115C-page 14
1995 Microchip Technology Inc.
5.4
Program Counter (PC) f2
See Section 4.2
5.5
Stack
See Section 4.3
5.6
Status Word Register (STATUS) f3
This register contains the arithmetic status of the ALU,
the RESET status.
The STATUS register can be destination for any
instruction like any other register. However, the status
bits are set after the following write. Furthermore, TO
and PD bits are not writable. Therefore, the result of an
instruction with STATUS register as destination may be
different than intended. For example, CLRF STATUS
will clear all bits except for TO and PD and then set the
Z bit and leave STATUS register as 000uu100 (where
u
= unchanged).
It is recommended, therefore, that only BCF, BSF and
MOVWF
instructions are used to alter the STATUS
registers because these instructions do not affect any
status bit.
For other instructions, affecting any status bits, see
Section "Instruction Set Summary" (Table 9-1).
FIGURE 5-6:
STATUS WORD REGISTER
C: Carry/borrow bit.
For ADDWF and ADDLW instructions.
1 =
0 =
A carry-out from the most significant bit of the result occurred
Note that a subtraction is executed by adding the two's
complement of the second operand. For rotate (RRF, RLF)
instructions, this bit is loaded with either the high or low order bit
of the source register.
No carry-out from the most significant bit of the result
DC: Digit carry/borrow bit
For ADDWF and ADDLW instructions.
1 =
0 =
Z: Zero bit
1 =
0 =
PD: Power down bit
1 =
0 =
TO: Time-out bit
1 =
0 =
PA1:PA0: Two general purpose read/write bits for MTA854XX
PA2
PA1
PA0
TO
PD
ZDC
C
bit0
R/W
R
R/W
bit7
A carry-out from the 4th low order bit of the result occurred
No carry-out from the 4th low order bit of the result
The result of an arithmetic or logic operation is zero
The result of an arithmetic or logic operation is not zero
After power-up or by a CLRWDT instruction
By execution of the SLEEP instruction
After power-up and by the CLRWDT and SLEEP instruction
A watchdog timer time-out has occurred
PA2: General purpose read/write bit
TO, PD are uniquely set or cleared
W:
Writable
R:
Readable
U:
Unimplemented,
read as '0'
Address:
POR value:
Register:
STATUS
Note: For borrow the polarity is reversed.
In MTA858XX these are page select bits.
(reserved for future use)
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