參數資料
型號： MTA85811S-04I/SS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20
封裝： 0.209 INCH, PLASTIC, SSOP-20
文件頁數： 62/72頁
文件大?。?/td> 760K
代理商： MTA85811S-04I/SS
1995 Microchip Technology Inc.
DS40115C-page 65
MTA85XXX
INDEX
A
Absolute Maximum Ratings ............................................... 33
AC Characteristics (04, 10, 20) COM/IND ................... 37–39
Assembler .......................................................................... 63
B
Block Diagram
Chip .............................................................................. 5
I/O Pin ........................................................................ 17
On-Chip Reset Circuit ................................................ 27
RTCC (Simplified) ...................................................... 14
RTCC and WDT ......................................................... 21
Brown-Out Protection Circuit ............................................. 30
C
C Compiler (MP-C) ............................................................ 63
Code Protection ................................................................. 32
Configuration Fuses ........................................................... 32
D
Data Memory Map ............................................................. 10
DC Characteristics (04, 10, 20) COM/IND ................... 34–36
Development Support ........................................................ 60
Development Systems ....................................................... 63
E
External Power-On Reset Circuit ....................................... 30
F
Features Overview ............................................................... 1
File Register Descriptions
FSR ............................................................................ 16
INDF ........................................................................... 13
PC .............................................................................. 15
RTCC ......................................................................... 13
STATUS ..................................................................... 15
Fuzzy Logic Dev. System (
fuzzyTECH
-MP) ................... 63
I
I/O Ports ............................................................................. 17
Indirect Addressing ............................................................ 13
Instruction Set .................................................................... 22
M
MPASM Assembler ............................................................ 63
MP-C C Compiler ............................................................... 63
MPSIM Software Simulator ................................................ 63
O
OPTION Register ............................................................... 19
OTP Devices ........................................................................ 7
P
Package Information .................................................... 64, 65
Page Select (program memory) ........................................... 8
PD bit ................................................................................. 16
PICMASTER Probe ........................................................... 61
PICMASTER System Configuration ................................... 61
Pinout Information .......................................................... 1, 40
POR
Time-Out Sequence on Power-Up ............................. 29
Prescaler (RTCC/WDT) ............................................... 19, 21
Program Counter ................................................................. 8
Program memory map ......................................................... 9
Q
QTP Devices ........................................................................ 7
R
Real Time Clock/Counter (RTCC) ......................... 13, 14, 19
RESET ............................................................................... 20
S
Software Simulator (MPSIM) ............................................. 63
Stack .............................................................................. 9, 15
Status Register .................................................................. 15
T
Timing Diagrams
I/O Pin ........................................................................ 17
RTCC Timing ............................................................. 14
TO bit ................................................................................. 16
TRIS Registers .................................................................. 19
U
UV Erasable Devices ........................................................... 7
W
W Register ......................................................................... 19
WDT .................................................................................. 24
Table of Figures
Figure 2-1:
MTA85XXX Series Block Diagram ............... 5
Figure 2-2:
Clocks/Instruction Cycle ............................... 6
Figure 4-1:
Program Memory Organization MTA854XX. 9
Figure 4-2:
Program Memory Organization MTA858XX. 9
Figure 5-1:
Data Memory Map...................................... 10
Figure 5-2:
T0CKI Block Diagram (Simplified).............. 13
Figure 5-3:
T0CKI Timing: INT Clock/No Prescale ....... 13
Figure 5-4:
T0CKI Timing: INT Clock/Prescale 1:2....... 13
Figure 5-5:
T0CKI Timing With External Clock ............. 13
Figure 5-6:
Status WORD Register .............................. 14
Figure 5-7:
Equivalent Circuit For a Single I/O Pin ....... 16
Figure 5-8:
I/O Port Read/Write Timing ........................ 16
Figure 6-1:
OPTION Register ....................................... 18
Figure 8-1:
Block Diagram T0CKI/WDT Prescaler ....... 20
Figure 10-1:
Watchdog Timer Block Diagram................. 23
Figure 11-1:
Crystal /Ceramic Resonator Operation
(HS, XT or LP OSC Configuration)............. 24
Figure 11-2:
External Clock Input Operation
(HS, XT or LP OSC Mode) ......................... 24
Figure 11-3:
External Parallel Resonant Crystal
Oscillator Circuit ......................................... 25
Figure 11-4:
External Series Resonant Crystal
Oscillator Circuit ......................................... 25
Figure 11-5:
RC Oscillator Mode .................................... 25
Figure 12-1:
On-Chip Reset Circuit Block Diagram ........ 26
Figure 12-2:
Time-Out Sequence on Power-Up
(MCLR Not Tied to VDD): Case 1 ............... 28
Figure 12-3:
Time-Out Sequence on Power-Up
(MCLR Not Tied to VDD): Case 2 ............... 28
Figure 12-4:
Time-Out Sequence on Power-Up
(MCLR Tied to VDD) ................................... 28
Figure 12-5:
External Power-On Reset Circuit
(For Slow VDD Power-Up) .......................... 29
Figure 12-6:
Brown-Out Protection Circuit 1................... 29
Figure 12-7:
Brown-Out Protection Circuit 2................... 29
Figure 12-8:
Electrical Structure of the MCLR/VPP and
T0CKI Pins ................................................. 29
Figure 14-1:
Configuration Word .................................... 32
Figure 15-1:
Electrical Structure of I/O Pins (RA, RB) .... 39
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