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參數(shù)資料
| 型號： | MTD9N10ET4 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | JFETs |
| 英文描述： | 9 A, 100 V, 0.25 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | CASE 369A-13, DPAK-3 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 246K |
| 代理商： | MTD9N10ET4 |
MTD9N10E
http://onsemi.com
7
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.190
4.826
mm
inches
0.100
2.54
0.063
1.6
0.165
4.191
0.118
3.0
0.243
6.172
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RθJA, the
thermal resistance from the device junction to ambient, and
the operating temperature, TA. Using the values provided
on the data sheet, PD can be calculated as follows:
PD =
TJ(max) TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device. For a
DPAK device, PD is calculated as follows.
PD =
150
°C 25°C
71.4
°C/W
= 1.75 Watts
The 71.4
°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There
are other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the
area of the drain pad. By increasing the area of the drain
pad, the power dissipation can be increased. Although one
can almost double the power dissipation with this method,
one will be giving up area on the printed circuit board
which can defeat the purpose of using surface mount
technology. For example, a graph of RθJA versus drain pad
area is shown in Figure 15.
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
A, Area (square inches)
R
,
Thermal
Resistance,
Junction
to
Ambient
(C/W)
θ JA
°
80
100
60
40
20
10
8
6
4
2
0
3.0 Watts
5.0 Watts
TA = 25°C
1.75 Watts
Board Material = 0.0625″
G10/FR4, 2 oz Copper
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