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參數(shù)資料
| 型號： | MTV20N50E |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET 20 AMPERES 500 VOLTS RDS(on) = 0.240 OHM |
| 中文描述： | 20 A, 500 V, 0.24 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 273K |
| 代理商： | MTV20N50E |
5
Motorola TMOS Power MOSFET Transistor Device Data
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
I
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Figure 10. Stored Charge
0.54
0.7
0.86
TJ = 25
°
C
VGS = 0 V
0
16
20
12
0.94
0.78
0.62
8
4
RG, GATE RESISTANCE (OHMS)
1
10
100
1000
100
10
t
VDD = 250 V
ID = 20 A
VGS = 10 V
TJ = 25
°
C
tr
tf
td(off)
td(on)
500
V
400
300
200
100
0
0
8
6
0
QG, TOTAL GATE CHARGE (nC)
V
10
4
2
10
20
80
90
100
ID = 20 A
TJ = 25
°
C
VDS
30
40
50
60
70
Q3
Q1
Q2
QT
VGS
Figure 11. Diode Forward Voltage versus Current
0.74
0.9
0.82
0.66
0.5
0.58
0
4
8
12
16
20
IS = 20 A
dlS/dt = 100 A/
μ
s
VDD = 50 V
TJ = 25
°
C
1
3
4
5
7
ID, DRAIN CURRENT (AMPS)
2
2
6
18
Q
μ
R
6
0
14
10
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25
°
C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10
μ
s. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R
θ
JC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
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