參數(shù)資料
型號(hào)： MUPA64K16-15TJI
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP128
封裝： LQFP-128
文件頁(yè)數(shù)： 16/19頁(yè)
文件大小： 380K
代理商： MUPA64K16-15TJI
MUPA64K16 Alto Priority Queue Scheduler
MUSIC Semiconductors Confidential
6
Rev 0.3 Draft
Table 3: Relationship Among Registers
MR[2:0]
Number
Of
Queues
PQ
Lines
Used
Number of
UID Get
Registers
Number
Of Wrap
Registers
Number
Of Size
Registers
Width of
Size
Register
000
1
none
1
17 bits
001
2
PQ[0]
2
16 bits
010
4
PQ[1:0]
4
15 bits
011
8
PQ[2:0]
8
14 bits
100, 101
16
PQ[3:0]
16
13 bits
110, 111
As seen in Table 3, although the Size Register, Wrap
Register and UID Get Register are replicated 16
times, not all of these registers are accessible if the
MR value is less than four.
Table 4: Status Register
Bit 0
If Bit 0 is ‘1’ IKR and IDR are ready to
accept new values; If Bit 0 is ‘0’ if a
command has been issued, but execution
has not yet started.
Bit 1
If Bit 1 is ‘1’ MKR and MDR contain new
values to be read; If Bit 1 is reset to zero,
either the MKR or MDR registers are
read.
Bit 2
If Bit 2 is ‘1” the UPR is ready to accept a
new UID value.
Bit 3
If Bit 3 is ‘1’ any UGR contains a new UID
value to be read.
Bit 4
If Bit 4 is ‘1’ the most recent UID Get
operation completed and the associated
UID Get Register contains the new UID
value.
Bit
[20:5]
Bits [20:5] provide the status of the most
recent UID Get operation for each
individual UID Get Register. Bit 5 is ‘1’ if
the most recent UID Get operation
completed for queue zero, Bit 6 is ‘1’ if the
most recent UID Get operation completed
for queue one, and so forth.
The STR is read only. Bits 4:0 of the Status Register
can be read directly on pins STR[4:0].
Size Register (16 x 17 bits)
The Size Register (SR) contains the number of active
entries in the priority queue as selected by PQ[3:0].
Note that each SR ranges from zero to N, where N is
the maximum number of elements in the queue. Each
priority queues has its own SR. The size can be read
and a write to the SR sets the priority queue size to
zero. The SR is read only. A write to the SR will reset
its
value
to
zero
after
the
current
operation
completes. All SRs are initialized to zero.
Wrap Register (16 x 32 bits)
The Wrap Register (WR) contains the minimum key
value for the priority queue as selected by PQ[3:0]. If
the WR contains the value N, then N is considered to
be the smallest key value and N-1 is considered to be
the largest key value. Each priority queues has its
own WR. The WR is read/write, although the new
wrap value will not be used until after the current
operation completes. All WRs are initialized to zero.
UID Get Register (16 x 17 bits)
Each UID Get Register (UGR) contains an identifier
for the priority queue as selected by PQ[3:0]. A
separate UGR exists for each priority queue to allow
these identifiers to be generated in advance. The
minimum UID is zero and the maximum UID is one
less than the maximum number of elements for a
queue. The identifiers are unique only within a queue
and not among queues. Bits 15:0 contain the UID
value. Bit 16 indicates whether bits 15:0 are valid. Bit
17 indicates whether the UGR has a new value since
the last time that it was read. The UGRs are read
only registers.
UID Put Register (1 x 16 bits)
The UID Put Register (UPR) accepts identifiers that
are no longer in use so that they can be reused. The
unique identifier is returned to the free list of UIDs for
the priority queue selected by PQ[3:0]. The UPR is
write only register.
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