參數(shù)資料
型號： MV80C51C-20D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44
封裝： 1.40 MM HEIGHT, QFP-44
文件頁數(shù)： 144/170頁
文件大?。?/td> 4133K
代理商： MV80C51C-20D
75
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
When the ICR0 is used as TOP value (see description of the WGM03:0 bits located in the TCCR0A and the
TCCR0B Register), the ICP0 is disconnected and consequently the Input Capture function is disabled.
Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero
when TCCR0B is written.
Bits 4:3 – WGM03:2: Waveform Generation Mode
Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits set the clock source to be used by the Timer/Counter, see Figure 11-12 and Figure 11-
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
11.11.3
TCCR0C – Timer/Counter0 Control Register C
Bit 7 – FOC0A: Force Output Compare for Channel A
Bit 6 – FOC0B: Force Output Compare for Channel B
The FOC0A/FOC0B bits are only active when the WGM03:0 bits specifies a non-PWM mode. However, for ensur-
ing compatibility with future devices, these bits must be set to zero when TCCR0A is written when operating in a
PWM mode. When writing a logical one to the FOC0A/FOC0B bit, an immediate compare match is forced on the
Waveform Generation unit. The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that
the FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the COM0x1:0 bits that
determine the effect of the forced compare.
A FOC0A/FOC0B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match
(CTC) mode using OCR0A as TOP.
The FOC0A/FOC0B bits are always read as zero.
Table 11-6.
Clock Select Bit Description
CS02
CS01
CS00
Description
0
No clock source (Timer/Counter stopped)
00
1
clkI/O/1 (No prescaling)
01
0
clkI/O/8 (From prescaler)
01
1
clk
I/O/64 (From prescaler)
10
0
clkI/O/256 (From prescaler)
10
1
clkI/O/1024 (From prescaler)
1
0
External clock source on T0 pin. Clock on falling edge
1
External clock source on T0 pin. Clock on rising edge
Bit
765
4
3
210
FOC0A
FOC0B
–
TCCR0C
Read/Write
W
R
Initial Value
0
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